Kyoung Ik Cho

42.3: Transparent ZnO Thin Film Transistor for the Application of High Aperture Ratio Bottom Emission AM-OLED Display

We have fabricated 2.5″ QCIF+ bottom emission AM-OLED with aperture ratio of 59.6% using fully transparent ZnO-TFT array and highly conductive oxide/metal/oxide electrode for the first time. The bias stability of ZnO TFT was improved by optimizing ZnO deposition and first gate insulator process. Plasma free process for the gate insulator makes ZnO TFT very stable under electrical bias stress. The Vth shift was less than 0.3V after VDS=25 V and VGS=15 V application for 60 hours. Transparent ZnO TFT characteristics did not change noticeably under irradiation of visible light.

21.2: Al and Sn-Doped Zinc Indium Oxide Thin Film Transistors for AMOLED Back-Plane

We have fabricated the transparent bottom gate TFTs using Al and Sn-doped zinc indium oxide (AT-ZIO) as an active layer. The AT-ZIO active layer was deposited by RF magnetron sputtering at room temperature, and AT-ZIO TFT showed a field effect mobility of 15.6 cm2/Vs even before annealing. The mobility increased with increasing In2O3 content and post-annealing temperature. The AT-ZIO TFT exhibited afield effect mobility of 33 cm2/Vs, a sub-threshold swing of 0.08 V/dec, and an on/off current ratio of more than 109 after Al2O3 passivation and post-annealing. We have fabricated AMOLED panels with the bottom gate AT-ZIO TFT back-plane successfully.

Synthesis of bamboo-shaped carbon-nitrogen nanotubes using C2H2-NH3-Fe(CO)5 system

Aligned bamboo-shaped carbon–nitrogen nanotubes have been massively produced by the pyrolysis of iron pentacarbonyl (Fe(CO)5) and acetylene (C2H2) mixtures with ammonia (NH3) being the source of nitrogen. With nitrogen doping, the nanotubes have a bamboo-like structure and reveal degraded crystallinity of graphite sheets. Nitrogen plays a key role in generating compartment layers inside the nanotube. A base-growth model is adequate to explain the carbon–nitrogen nanotube growth.

Transparent ZnO-TFT arrays fabricated by atomic layer deposition

Transparent ZnO thin film transistor (TFT) array of 176 X 144 (106 dpi) was fabricated on glass substrate. The V th of the TFT with inverted coplanar structure is about 0.8 V and the mobility is 1.13 cm 2 /V s. The active layer (ZnO), gate insulator (Al 2 O 3 ), and source-drain electrode (ZnO:Al) were deposited by atomic layer deposition. We also compared the performance of TFTs fabricated by lift-off and wet-etching process as the patterning processes of ZnO layer. The carrier density of the ZnO layer was carefully adjusted to reduce off-current of TFT. Good contact with small contact resistance was formed between the active layer and the source-drain electrode.

Diameter-controlled growth of carbon nanotubes using thermal chemical vapor deposition

The diameter and the growth rate of vertically aligned carbon nanotubes (CNTs) are controlled by modulating the size of catalytic particles using thermal chemical vapor deposition (CVD). The size of iron catalytic particles deposited on silicon oxide substrate is varied in a controlled manner by adjusting the condition of ammonia pretreatment. We found an inverse relation between the diameter and growth rate of carbon nanotubes. As the diameter increases, the compartment layers of bamboo-shaped carbon nanotubes appear more frequently, which is suitably explained by the base growth mechanism.

Impact of device configuration on the temperature instability of Al–Zn–Sn–O thin film transistors

We compared the effect of the temperature on the device stability of Al–Zn–Sn–O (AZTO) thin film transistors (TFTs) with top gate and bottom gate architectures. While the bottom gate device without any passivation layer on the AZTO channel layer showed a large threshold voltage (Vth) shift of 1.6 V after heating it from 298 to 398 K, the naturally passivated top gate device exhibited a smaller Vth shift of 0.6 V. This different behavior is discussed based on the concept of the thermal activation energy of the subthreshold drain current. It is proposed that the suitable passivation and lower interfacial trap density for the top gate TFT are responsible for its superior temperature stability compared to the bottom gate device.

Microstructural properties of phosphorus-doped p-type ZnO grown by radio-frequency magnetron sputtering

Phosphorus (P)-doped ZnO thin films were grown by radio-frequency magnetron sputtering to study the microstructural properties of p-type ZnO. As-grown P-doped ZnO, a semi-insulator, was converted to p-type ZnO after being annealed at 800°C in an N2 ambient. X-ray diffraction, secondary-ion-mass spectrometry, and Hall effect measurements indicated that P2O5 phases in as-grown P-doped ZnO disappeared after thermal annealing to form a substitutional P at an O lattice site, which acts as an acceptor in P-doped ZnO. Transmission electron microscopy showed that the formation of stacking faults was facilitated to release the strain in P-doped ZnO during post-thermal annealing.

Electrical Properties of SrBi2Ta2O9/Insulator/Si Structures with Various Insulators

The electrical properties of metal/ferroelectric/insulator/semiconductor (MFIS) structures with various insulators were investigated. Layers of Si3N4/SiO2 (NO) formed by thermal oxidation and low pressure chemical vapor deposition (LPCVD) and Al2O3 layers deposited by atomic layer deposition (ALD) were used as inter-dielectric layers. SrBi2Ta2O9 (SBT) films used as ferroelectric layers were prepared by metal organic decomposition (MOD). The capacitance-voltage (C–V) curves including the memory window were affected by varying the annealing temperature for SBT films. Memory windows for MFIS structures with NO inter-dielectrics in the range of 0.75–1.2 V were maintained up to annealing temperatures of 900°C. The width of the memory window in C–V curves for MFISs using thin Al2O3 layers decreases with increasing annealing temperature. Therefore, the selection of a good insulator and parameter control are required for the use of MFIS-ferroelectric random access memories (FRAMs).

Photolithography-based carbon nanotubes patterning for field emission displays

Carbon nanotubes (CNTs) emitters were successfully patterned in small pixels (50×50 μm2) by using photolithography process on a hard metal electrode for field emission displays (FEDs) application. The CNTs particles in the patterned pixels were uniformly distributed on 2-inch diagonal substrates. The maximum diameter of CNTs particles could be controlled less than 20 μm. After patterning and heat treatment process below 300°C, most of CNTs bundles on the cathode electrode were aligned perpendicular to the substrates. The threshold electric field of emission for patterned CNTs was about 4.2 V μm−1 and the field enhancement factor derived from the Fowler–Nordheim plots of the electron emissions was about 100 000 in the high voltage region. This newly developed process can be applicable to field emitter arrays for high resolution FEDs.

Characterizations of Fine-pitched Carbon Nanotube Pixels for Field Emitter Arrays

Fine-pitched carbon nanotube (CNT) pixels for field emitter arrays were patterned using a lift-off process. Compared with the conventional screen-printing method, this lift-off process provides a small feature size of 195 µm×80 µm pixels in emitter arrays. The field emission properties of patterned pixels are highly dependent on surface morphology. The buried carbon nanotubes from the surface barely contribute to field emission in a low electric field range. By using a proper formulation of carbon nanotube slurry for emitters in the patterning layer, we were able to obtain carbon nanotube pixels in which most of carbon nanotubes protruded from the surface layer of patterns after a final heat treatment, to burn out the organic binders at 300°C. Their turn-on field was determined to be less than 2.2 V/µm and the current density was 3.2 mA/cm2 at 3.7 V/µm. This lift-off process has the potential for use as an inexpensive patterning method for fine-pitched emitter array on a large substrate.