Mindaugas Drazdziulis

Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration

We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circuit-simulation backend used to obtain static leakage power values of all basic memory components. The method is flexible in that memory size is an arbitrary parameter. In a comparison to circuit-level simulations (Hspice) of complete 2 KBytes and 8 KBytes 6T-SRAM memories implemented both in 0.13-mum and 65-nm (BPTM) bulk CMOS processes, the proposed method shows a high accuracy in estimating leakage power

A low-leakage twin-precision multiplier using reconfigurable power gating

A twin-precision multiplier that uses reconfigurable power gating is presented. Employing power cut-off techniques in independently controlled power-gating regions yields significant static leakage reductions when half-precision multiplications are carried out. In comparison to a conventional 8-bit tree multiplier, the power overhead of a 16-bit twin-precision multiplier operating at 8-bit precision has been reduced by 53% when reconfigurable power gating based on the SCCMOS power cut-off technique was applied.

A gate leakage reduction strategy for future CMOS circuits

We show that a technique previously introduced for sub-threshold leakage reduction can be effectively used to reduce gate leakage dissipation in future CMOS circuits operating in stand-by mode. The technique gave one order of magnitude gate leakage savings with a certain input pattern for the evaluated two-input NAND gate. Also, we make a detailed analysis of mechanisms causing different direct oxide tunnelling currents that contributes to gate leakage power dissipation in future CMOS circuits.

Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays

We propose a methodology and power models for an accurate high-level power estimation of physically partitioned and power-gated SRAM arrays. The models offer accurate estimation of both dynamic and leakage power, including the power dissipation due to emerging leakage mechanisms such as gate oxide tunneling, for partitioned arrays that deploy data-retaining sleep techniques for leakage reduction. Using the proposed methodology, dynamic, leakage and total power of partitioned SRAM arrays can be estimated with a 97% accuracy in comparison to the power obtained by running full circuit-level simulations

A power cut-off technique for gate leakage suppression [CMOS logic circuits]

Gate leakage power dissipation is predicted to overtake subthreshold leakage power within the next few years thus adding further problems for designers trying to meet a strict power budget. In this paper, a power cut-off technique is proposed, which in sleep mode suppresses not only subthreshold leakage but also gate leakage. The proposed technique displays a combination of low total leakage power and short wake-up time.

Overdrive Power-Gating Techniques for Total Power Minimization

We investigate how to apply power-gating techniques to logic circuits for maximal total power reduction. We compare techniques that employ overdriven low-Vt power switches (SCCMOS) with those employing high-Vt power switches (MTCMOS). When sized under the same constraints for maximum voltage drop in active mode, MTCMOS has 10% shorter total wake-up time compared to SCCMOS. However, SCCMOS performs better in saving power than MTCMOS as logic circuit blocks increase in size and have increasing lengths of idle time. To obtain maximal power savings in idle mode, we introduce a process variation tolerant control circuit for overdrive voltage generators that offers a 2.7times power savings improvement for a 130-nm process.

Evaluation of power cut-off techniques in the presence of gate leakage

We consider gate leakage next to subthreshold leakage currents in power-saving techniques for future CMOS circuits. Two recently introduced power cut-off techniques are analyzed and compared with respect to the total leakage current using Berkeley PTM. The results show that the efficiency of techniques having logic circuits alternately connected to external supply and ground can drastically degrade when gate tunneling currents become significant.

High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process

In this paper, we validate our previously proposed high- level power estimation models for a 65-nm BPTM process, using a physically partitioned 2-kB 6T-SRAM array. Also, we describe a new probing methodology that allows us to accurately capture not only subthreshold leakage, but also all other significant leakage mechanisms. By combining the probing methodology and the power models, we can estimate dynamic, leakage and total power of the partitioned 2-kB memory array with a 97% accuracy of that of full circuit-level simulations of the entire array. We also discuss the effect of partitioning on SRAM array power with respect to process technology scaling: Partitioning has the effect that leakage power constitutes an increasing fraction of total memory power, emphasizing the need to accurately capture leakage power in SRAM power models.