Minh Quang Do

Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration

We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circuit-simulation backend used to obtain static leakage power values of all basic memory components. The method is flexible in that memory size is an arbitrary parameter. In a comparison to circuit-level simulations (Hspice) of complete 2 KBytes and 8 KBytes 6T-SRAM memories implemented both in 0.13-mum and 65-nm (BPTM) bulk CMOS processes, the proposed method shows a high accuracy in estimating leakage power

Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays

We propose a methodology and power models for an accurate high-level power estimation of physically partitioned and power-gated SRAM arrays. The models offer accurate estimation of both dynamic and leakage power, including the power dissipation due to emerging leakage mechanisms such as gate oxide tunneling, for partitioned arrays that deploy data-retaining sleep techniques for leakage reduction. Using the proposed methodology, dynamic, leakage and total power of partitioned SRAM arrays can be estimated with a 97% accuracy in comparison to the power obtained by running full circuit-level simulations

Table-Based Total Power Consumption Estimation of Memory Arrays for Architects

In this paper, we propose the White-box Table-based Total Power Consumption (WTTPC) estimation approach that offers both rapid and accurate architecture-level power estimation models for some processor components with regular structures, such as SRAM arrays, based on WTTPC-tables of power values. A comparison of power estimates obtained from the proposed approach against circuit-level HSPICE power values for a 64-b conventional 6T-SRAM memory array implemented in a commercial 0.13-um CMOS technology process shows a 98% accuracy of the WTTPC approach.

High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process

In this paper, we validate our previously proposed high- level power estimation models for a 65-nm BPTM process, using a physically partitioned 2-kB 6T-SRAM array. Also, we describe a new probing methodology that allows us to accurately capture not only subthreshold leakage, but also all other significant leakage mechanisms. By combining the probing methodology and the power models, we can estimate dynamic, leakage and total power of the partitioned 2-kB memory array with a 97% accuracy of that of full circuit-level simulations of the entire array. We also discuss the effect of partitioning on SRAM array power with respect to process technology scaling: Partitioning has the effect that leakage power constitutes an increasing fraction of total memory power, emphasizing the need to accurately capture leakage power in SRAM power models.