Ming Chen

Comprehensive Study on the Total Dose Effects in a 180-nm CMOS Technology

The effects of total ionizing on a 180-nm CMOS technology are comprehensively studied. Firstly, we show new results on the hump effect which has strong relationship to the STI corner oxide thickness. Secondly, the leakage current degradation in various devices after radiation is investigated. For the intra-device leakage, both body doping concentration and STI corner thickness play very important roles. For the inter-device leakage, due to the low electric field at the STI bottom, it is found to be insensitive to ionizing radiation. Thirdly, a method for extracting the effective threshold voltage of the sidewall parasitic transistor is proposed by studying the leakage output characteristics. Finally, we find that the drain saturation current increases in NMOS transistors after radiation, especially in the narrow-channel ones.

Bias dependence of TID radiation responses of 0.13 μm partially depleted SOI NMOSFETs

Abstract The bias dependence of total ionizing dose (TID) radiation responses of 0.13xa0μm Partially Depleted (PD) SOI NMOSFETs is presented. Experiments and three dimensional (3D) simulations are used to analyze the buildup of trapped charge in the STI oxide as well as in the buried oxide (BOX) and its impact on the negative shift of back-gate threshold voltage and subthreshold hump. It is demonstrated that the worst-case bias conditions for the largest back-gate threshold voltage shift and increase of the off-state leakage current (or the negative shift of back-gate subthreshold hump) are different. The radiation-induced positive trapped charge in the BOX can fully deplete the body silicon for input/output (I/O) NMOSFETs as a result of the lower body doping concentration, giving rise to the coupling effect between the front-gate and back-gate threshold voltage shift.

Total Ionizing Dose Enhanced DIBL Effect for Deep Submicron NMOSFET

Radiation enhanced drain induced barrier lowering (DIBL) effect under different bias conditions was experimentally observed and verified by 3D simulation for deep submicron MOSFETs with shallow trench isolation (STI) oxides. The off-state leakage current increased significantly after total ionizing dose (TID) above 200 krad(Si) for PASS ,OFF and ON bias condition. The irradiated devices exhibited enhanced DIBL effect, that is the off-state leakage current increases with drain voltage and DIBL parameter increases with TID. The oxide trapped charge in the STI sidewall enhances the DIBL by decreasing the drain to gate coupling, enhancing the electric field near the STI corner, and increasing the surface potential of lowly doped substrate along STI sidewall. A simple dipole theory describing the enhanced DIBL phenomenon is introduced. The phenomenon is a result of the electrostatic effect, which concentrates drain field on channel into the source along shallow trench isolation oxide. Effective non-uniform charge distribution is applied in the 3D simulation for the radiation enhanced DIBL effect. Good agreement between experiment and simulation results is demonstrated.

Improving Total Dose Tolerance of Buried Oxides in SOI Wafers by Multiple-Step

A modified hardening technique is proposed to improve the total dose hardness of buried oxides in silicon-on-insulator (SOI) technologies using multiple-step Si+ ion implantation. Each implanting step introduces a dose of 5 ×1015/cm2 into buried oxides which creates an amorphous/crystalline (a/c) interface within the top Si layer. Inter-implant rapid thermal annealing (RTA) removes implant-induced lattice damages by moving a/c interface towards top silicon surface. The thermal processes between implant steps prevent top silicon layers from total amorphization which is a kind of unrecoverable damage in the single-step method. High Resolution X-Ray Diffraction (HRXRD) technique is exploited to inspect the lattice quality of top silicon in light of a slight crystal orientation mismatch during bonded-wafer fabrication. Pseudo-mos transistor characterization technique confirms the hardening capability of the new method.

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The effects of total ionizing dose (TID) irradiation on the inter-device and intra-device leakage current in a 180-nm flash memory technology are investigated. The positive oxide trapped charge in the shallow trench isolation (STI) oxide is responsible for the punch-through leakage increase and punch-through voltage decrease. Nonuniform radiation-induced oxide trapped charge distribution along the STI sidewall is introduced to analyze the radiation responses of input/output (I/O) device and high voltage (HV) device. At low dose level, the inversion near the STI corner caused by the trapped charge occurs more easily due to the lower doping concentration in this region, which gives rise to the subthreshold hump effect. With total dose level increase, more charge at deep region of the STI oxide is accumulated, predominating the intra-device off-state leakage current. It has been discussed that the STI corner scheme and substrate doping profile play important roles on influencing the device’s performance after radiation.

Implantation

A first order model of radiation induced narrow-channel effect (RINCE) is developed by applying charge conservation principle to calculate threshold voltage shift due to total ionizing dose (TID) irradiation. The model provides a way for extracting effective sheet charge density along shallow trench isolation (STI) sidewalls.

Radiation-induced shallow trench isolation leakage in 180-nm flash memory technology

Abstract The response of single flash cell in a 180-nm flash technology to total ionizing dose (TID) is studied. The results indicate that the erased cell flips at a dose level of 100xa0krad(Si), whereas the programmed cell does not even at the dose level up to 1xa0Mrad(Si). This asymmetric phenomenon is attributed to the difference between the reference current of the comparator circuit and the intrinsic current of the flash cell. For the first time, we show that the irradiation-induced flash cell drain-current variation does not saturate at the intrinsic value, i.e. the drain current of a device with neutrally charged floating gate. After degrading to the intrinsic state, the read current of the erased cell gradually increases while the programmed cell continues to increase and then slightly drops back. Radiation tolerance comparison of single flash cell, I/O transistors and high-voltage (HV) transistors demonstrates that HV NMOS is most susceptible to ionizing radiation. The radiation tolerance of the circuit level is also evaluated from the elementary devices.

Simple Method for Extracting Effective Sheet Charge Density Along STI Sidewalls Due to Radiation

Total ionizing dose (TID) response in core, input/output (I/O) and high voltage (HV) transistors for 180 nm flash memory technology is comprehensively investigated. Great influence by irradiation is observed for all these transistors, including threshold voltage shift, appearance of subthreshold hump effect and increase of off-state leakage current. Also, we found that the higher the drain voltage, the larger increase of the off-state leakage, which is well known as radiation enhanced drain induced barrier lowering (DIBL) effect. Radiation enhanced DIBL effect leads to worse characteristic degradation of transistor. The HV transistor is the most sensitive parts in flash memory control circuitry.

Total ionizing dose effects in elementary devices for 180-nm flash technologies

A new phenomenon, for the first time, shows that radiation-induced body effect factor decrease in NMOS transistors is presented. The results indicate that body effect factor shift decreases as the total ionizing dose (TID) level increases in NMOS transistors, especially in the narrow-channel ones, which can be considered as one of the radiation-induced narrow-channel effect (RINCE). A first-order model is developed by applying charge conservation principle. Good agreement is obtained by comparing the modeling with experimental results. Finally, some implications to mitigate the RINCE effect are discussed.

Comparison of TID response in core, input/output and high voltage transistors for flash memory

A reverse substrate bias is known to increase the threshold voltage and reduce the off-state leakage current, which is of great interest from a radiation perspective in space applications. In this work, substrate biases during both irradiation and post-irradiation test on the impacts of total ionizing dose effects in a 180 nm CMOS technology are studied. The results indicate that a negative substrate bias during irradiation impairs the radiation hardness while a negative substrate bias during post-irradiation test improves the radiation hardness for nMOS transistors. A simple model is proposed to discuss the net result including the both effects. We find that the substrate bias for radiation hardening does not always work in some special conditions, such as the device with very low body doping and the STI which is very sensitive to the electric field for the buildup of charge.