Zhangli Liu

Comprehensive Study on the Total Dose Effects in a 180-nm CMOS Technology

The effects of total ionizing on a 180-nm CMOS technology are comprehensively studied. Firstly, we show new results on the hump effect which has strong relationship to the STI corner oxide thickness. Secondly, the leakage current degradation in various devices after radiation is investigated. For the intra-device leakage, both body doping concentration and STI corner thickness play very important roles. For the inter-device leakage, due to the low electric field at the STI bottom, it is found to be insensitive to ionizing radiation. Thirdly, a method for extracting the effective threshold voltage of the sidewall parasitic transistor is proposed by studying the leakage output characteristics. Finally, we find that the drain saturation current increases in NMOS transistors after radiation, especially in the narrow-channel ones.

Total Ionizing Dose Enhanced DIBL Effect for Deep Submicron NMOSFET

Radiation enhanced drain induced barrier lowering (DIBL) effect under different bias conditions was experimentally observed and verified by 3D simulation for deep submicron MOSFETs with shallow trench isolation (STI) oxides. The off-state leakage current increased significantly after total ionizing dose (TID) above 200 krad(Si) for PASS ,OFF and ON bias condition. The irradiated devices exhibited enhanced DIBL effect, that is the off-state leakage current increases with drain voltage and DIBL parameter increases with TID. The oxide trapped charge in the STI sidewall enhances the DIBL by decreasing the drain to gate coupling, enhancing the electric field near the STI corner, and increasing the surface potential of lowly doped substrate along STI sidewall. A simple dipole theory describing the enhanced DIBL phenomenon is introduced. The phenomenon is a result of the electrostatic effect, which concentrates drain field on channel into the source along shallow trench isolation oxide. Effective non-uniform charge distribution is applied in the 3D simulation for the radiation enhanced DIBL effect. Good agreement between experiment and simulation results is demonstrated.

Radiation-induced shallow trench isolation leakage in 180-nm flash memory technology

The effects of total ionizing dose (TID) irradiation on the inter-device and intra-device leakage current in a 180-nm flash memory technology are investigated. The positive oxide trapped charge in the shallow trench isolation (STI) oxide is responsible for the punch-through leakage increase and punch-through voltage decrease. Nonuniform radiation-induced oxide trapped charge distribution along the STI sidewall is introduced to analyze the radiation responses of input/output (I/O) device and high voltage (HV) device. At low dose level, the inversion near the STI corner caused by the trapped charge occurs more easily due to the lower doping concentration in this region, which gives rise to the subthreshold hump effect. With total dose level increase, more charge at deep region of the STI oxide is accumulated, predominating the intra-device off-state leakage current. It has been discussed that the STI corner scheme and substrate doping profile play important roles on influencing the device’s performance after radiation.

Simple Method for Extracting Effective Sheet Charge Density Along STI Sidewalls Due to Radiation

A first order model of radiation induced narrow-channel effect (RINCE) is developed by applying charge conservation principle to calculate threshold voltage shift due to total ionizing dose (TID) irradiation. The model provides a way for extracting effective sheet charge density along shallow trench isolation (STI) sidewalls.

Comparison of TID response in core, input/output and high voltage transistors for flash memory

Total ionizing dose (TID) response in core, input/output (I/O) and high voltage (HV) transistors for 180 nm flash memory technology is comprehensively investigated. Great influence by irradiation is observed for all these transistors, including threshold voltage shift, appearance of subthreshold hump effect and increase of off-state leakage current. Also, we found that the higher the drain voltage, the larger increase of the off-state leakage, which is well known as radiation enhanced drain induced barrier lowering (DIBL) effect. Radiation enhanced DIBL effect leads to worse characteristic degradation of transistor. The HV transistor is the most sensitive parts in flash memory control circuitry.

The impact of total ionizing radiation on body effect

A new phenomenon, for the first time, shows that radiation-induced body effect factor decrease in NMOS transistors is presented. The results indicate that body effect factor shift decreases as the total ionizing dose (TID) level increases in NMOS transistors, especially in the narrow-channel ones, which can be considered as one of the radiation-induced narrow-channel effect (RINCE). A first-order model is developed by applying charge conservation principle. Good agreement is obtained by comparing the modeling with experimental results. Finally, some implications to mitigate the RINCE effect are discussed.

Radiation Hardening by Applying Substrate Bias

A reverse substrate bias is known to increase the threshold voltage and reduce the off-state leakage current, which is of great interest from a radiation perspective in space applications. In this work, substrate biases during both irradiation and post-irradiation test on the impacts of total ionizing dose effects in a 180 nm CMOS technology are studied. The results indicate that a negative substrate bias during irradiation impairs the radiation hardness while a negative substrate bias during post-irradiation test improves the radiation hardness for nMOS transistors. A simple model is proposed to discuss the net result including the both effects. We find that the substrate bias for radiation hardening does not always work in some special conditions, such as the device with very low body doping and the STI which is very sensitive to the electric field for the buildup of charge.

Influence of poly region extended into field oxide on total ionizing dose effect for deep submicron MOSFET

Deep submicron technology devices with different width/length were exposed by gamma ray irradiation. Different total ionizing dose (TID) effects were observed for the wide and narrow channel device. Large increase of off-state leakage was observed for the wide channel device under radiation. However, insignificantly increase of off-state leakage was observed for the narrow channel one. The simulation result of potential distribution in the shallow trench isolation (STI) has shown that the influence of poly region extended into field oxide on the devices radiation response. The oxide trapped charge in the top and down region of the STI plays an important role in the different TID responses. A negative substrate bias during irradiation can give us more information about the charge distribution along the STI sidewall. By introducing non-uniform charge along the STI sidewall in the three dimension (3D) simulation, good agreement between the experiment and simulation result is demonstrated.

Impact of within-wafer process variability on radiation response

The impact of sample-to-sample variability on total ionizing dose (TID) response within-wafer for a 180-nm CMOS technology has been studied. Large variations in leakage current and threshold voltage shift after irradiation are observed. These variations are mainly contributed to the process variability. The process steps which cause TID response variation are preliminarily discussed.

Radiation induced inter-device leakage degradation

The evolution of inter-device leakage current with total ionizing dose in transistors in 180 nm generation technologies is studied with an N-type poly-gate field device (PFD) that uses the shallow trench isolation as an effective gate oxide. The overall radiation response of these structures is determined by the trapped charge in the oxide. The impacts of different bias conditions during irradiation on the inter-device leakage current are studied for the first time in this work, which demonstrates that the worst condition is the same as traditional NMOS transistors. Moreover, the two-dimensional technology computer-aided design simulation is used to understand the bias dependence.