Ming-Haw Jing

Reconfigurable system for high-speed and diversified AES using FPGA

In this article, we present a FPGA-based reconfigurable system for the advanced encryption standard (AES) algorithm. This proposed design, called diversified AES (DAES), has the variations of four parameters: the field irreducible polynomial, the affine transformation in the SubBytes, the offsets in the ShiftRows, and the polynomial in the MixColumns. The advantage of such variations in the AES system is that they increase the strength regarding internal or external attacks. We also use straightforward architecture - look-up tables - for encryption and decryption to lead this system simple and high-speed using field programmable gate arrays (FPGAs).

The diversity study of AES on FPGA application

In the applications of AES, the long-term robustness/reliability during the period of operation should be taken into serious considerations. From such considerations, one may initiate the requirements of the design for diversity against break through from outside. In system design, the use of reconfigurable FPGA can provide higher level of flexibility. In this paper, the proposed system uses different generators, various transforms, modules and algorithms to enhance the randomization of the ciphertext. It is also a challenge to improve the system flexibility and to get a more secure design in the AES system. Several reconfigurable modules are developed on our integrated test-bench.

The secure DAES design for embedded system application

Recently, Advanced Encryption Standard (AES) has become one of the major symmetric encryption algorithms used in the embedded system applications. Many researches extended use of the algorithm of AES for system security. In this paper, we propose a diversified AES (DAES) to create more variations. In the architecture of the DAES, the diversity results from the modification of the parameters of DAES. In the process of system design, the additional parameters may not only cause operational complexity but also influence the security. In this article, a method to measure the security of DAES is also provided. We propose a strategy to optimize the design of the DAES with higher security from the scope of S-box via repeating property and MixColumn polynomials via branch number. During the analysis procedure, the size of embedded program may also be reduced.

High-speed low-complexity Golay decoder based on syndrome-weight determination

In this paper, a very high-throughput and area efficient hardware decoder of the binary (23, 12, 7) Golay code is presented. The key feature of this proposed algorithm is fast determination of the error positions through the analysis on the weight of syndromes without large operations of finite fields. Comparing with the algorithm using one syndrome, the proposed algorithm is more suitable for the parallel hardware design by using two syndromes. For some common FPGA technology the complete system occupies only 666 logic elements and the time delay is 25.9 ns; for a 0.18-μm CMOS technology the result is a 0.026 mm2 area and a 2.58 Gbps throughput.

Design of simple and high speed VLSI core for the protection of mass storages

This paper presents a research to strengthen the using of embedded system memory, including: Flash memory, SRAM, DRAM etc. For increasing the reliability on data storage, we use the conventional fault-tolerant mechanisms-Mirror and CRC techniques to carry out the forward protection at first. Furthermore we use the encryption and Reed-Solomon code to improve the function at back end. This article designs a simple and high speed solution based on the finite field arithmetic, let the fault-tolerant facility can tolerate one-bit error from multiple bit error or multiple column error on common memories. Then we advanced improve the speed problem of Reed-Solomon code in coding, and develop an efficient way in the VLSI architecture. Finally we adopt the embedded system of DE2 to develop the co-design coding environment to provide a complete and high reliability scheme.

A new decoder for binary quadratic residue code with irreducible generator polynomial

The binary quadratic residue (QR) codes have nice distance property, but they are difficult to decode for the insufficient consecutive syndromes. The author used the Lagrange interpolation formula to calculate the needed primary unknown syndrome for the binary QR code. In this paper, we propose an efficient hardware architecture to implement this method, and decode the binary QR code by using the well-developed Berlekamp-Massey algorithm and Chien search.

Another Look at the Sequential Multiplier over Normal Bases

The Massey-Omura multiplier is a well-known sequential multiplier over finite fields GF(2m), which can perform multiplication in m clock cycles for the normal basis. In this article, the authors propose a new architecture to carry out the sequential multiplier using normal basis. The time complexity in each cycle of this new multiplier is O(1) and the number of inputs is lower down to m+1, instead of 2m, which is the number needed for most previous multipliers. These merits make it easier to the VLSI implementation

A fast parallel (23, 12, 7) QR decoder based on syndrome-weight determination

In this paper, a time-area efficient hardware decoder of the (23, 12, 7) quadratic residue code, or Golay code, is presented. The key feature of this proposed algorithm lies in fast determination of error positions through the analysis on the weight of syndromes without large operations in finite fields. Comparing with the algorithm using one syndrome, the proposed algorithm is more suitable for the parallel hardware design by using two syndromes. Based on an Altera Cyclone II field-programmable gate array (FPGA) device (EP2C35F484C6), the area cost and the time delay of the complete system are reduced by up to 86.4% and 22.5%, respectively. Using the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-@mm complementary metal-oxide-semiconductor (CMOS) standard cell library, the proposed decoder is 91.8% smaller and 8.3% faster.

Syndrome-weight decoder for general binary quadratic residue codes

Recently, a novel decoding procedure which is called the syndrome-weight determination for the Golay code, or the (23, 12, 7) quadratic residue code, was proposed by Chang et al. This method is not only very simple in principle but also suitable for the parallel hardware design. Furthermore, to develop a universal decoding algorithm for arbitrary binary quadratic residue codes is very important. In this paper, a simplified decoder for the general binary quadratic residue codes of different sizes is developed that is modified by the Changs decoding scheme. Because of its regular property, the proposed decoder is suitable not only for software design but also for hardware development.

The feasibility study of designing a FPGA multiplier-core on finite field

In digital system development, the CPLD/FPGA is usually used to implement basic function blocks for the purposes of testing, integration and IP proof. The advantages of CPLD/FPGA are high efficiency, flexibility and easy reconfiguration. Taking AES as an example, this application needs more flexible transformations to design for diversity. In order to meet such requirements without declining the performance, a modified architecture of FPGA is proposed to increase the overall efficiency and keep high throughput. A finite field multiplier is provided for the explanation of the newly developed core. The parallel and pipelined design in FPGA can replace high-speed VLSI chip with dynamic reconfigurability.