Zih-Heng Chen

Reconfigurable system for high-speed and diversified AES using FPGA

In this article, we present a FPGA-based reconfigurable system for the advanced encryption standard (AES) algorithm. This proposed design, called diversified AES (DAES), has the variations of four parameters: the field irreducible polynomial, the affine transformation in the SubBytes, the offsets in the ShiftRows, and the polynomial in the MixColumns. The advantage of such variations in the AES system is that they increase the strength regarding internal or external attacks. We also use straightforward architecture - look-up tables - for encryption and decryption to lead this system simple and high-speed using field programmable gate arrays (FPGAs).

Diversified Mixcolumn transformation of AES

In the Rijndael, one can replace some variations to produce different ciphers, including the irreducible polynomial, the affine transformation in the SubByte, the offsets in the ShiftRow, and the polynomial in the MixColumn, to increase the variety of the Advanced Encryption Standard (AES) algorithm. In this article we present three types of MixColumn polynomials that can be easily provided diversified selections of the AES algorithm.

New viewpoint of bit-serial/parallel normal basis multipliers using irreducible all-one polynomial

Recently, normal bases have been an appealing technique for hardware implementation in many applications, especially when finite fields are very large, such as the public key cryptosystems. In this article, a new viewpoint is introduced for performing the multiplication in the normal basis representation over binary field where the field defining irreducible polynomial is an all-one polynomial. The proposed multipliers carry out the normal basis multiplication by using extended polynomial basis multiplier to construct two architectures. These two classes of architectures are in bit-serial and bit-parallel which reduce the cost of space and time respectively

Low Complexity Architecture for Multiplicative Inversion in GF(2m)

The multiplicative inversion in finite field is much more complex than all field arithmetic operations. In this paper, a design of a simpler inversion module with lower complexity in GF(2m) using standard basis is proposed. It has the major improvement comparing with the design proposed by Wang et al. and Dinh et al. The implementations of those algorithms are examined in detail using 0.18-mum CMOS technology. The proposed method results in reduction of area requirement by 28% to 48% when m is between 3 and 12

The secure DAES design for embedded system application

Recently, Advanced Encryption Standard (AES) has become one of the major symmetric encryption algorithms used in the embedded system applications. Many researches extended use of the algorithm of AES for system security. In this paper, we propose a diversified AES (DAES) to create more variations. In the architecture of the DAES, the diversity results from the modification of the parameters of DAES. In the process of system design, the additional parameters may not only cause operational complexity but also influence the security. In this article, a method to measure the security of DAES is also provided. We propose a strategy to optimize the design of the DAES with higher security from the scope of S-box via repeating property and MixColumn polynomials via branch number. During the analysis procedure, the size of embedded program may also be reduced.

A Result on Zetterberg Codes

The family of Zetterberg codes with parameters (2u+1, 2u+1-2u) for even u is one of the best known double error correcting codes because of their large code rate and high decoding speed. In this letter, we prove that when u is odd, Zetterberg codes can correct all errors of weight at most two with only 2u+1 exceptions. Moreover, by multiplying (x-1) to the generator polynomials of Zetterberg codes with u odd, the cyclic codes generated are two-error correctable. A decoding algorithm is developed for the new family of Zetterberg codes.

High-speed low-complexity Golay decoder based on syndrome-weight determination

In this paper, a very high-throughput and area efficient hardware decoder of the binary (23, 12, 7) Golay code is presented. The key feature of this proposed algorithm is fast determination of the error positions through the analysis on the weight of syndromes without large operations of finite fields. Comparing with the algorithm using one syndrome, the proposed algorithm is more suitable for the parallel hardware design by using two syndromes. For some common FPGA technology the complete system occupies only 666 logic elements and the time delay is 25.9 ns; for a 0.18-μm CMOS technology the result is a 0.026 mm2 area and a 2.58 Gbps throughput.

Design of simple and high speed VLSI core for the protection of mass storages

This paper presents a research to strengthen the using of embedded system memory, including: Flash memory, SRAM, DRAM etc. For increasing the reliability on data storage, we use the conventional fault-tolerant mechanisms-Mirror and CRC techniques to carry out the forward protection at first. Furthermore we use the encryption and Reed-Solomon code to improve the function at back end. This article designs a simple and high speed solution based on the finite field arithmetic, let the fault-tolerant facility can tolerate one-bit error from multiple bit error or multiple column error on common memories. Then we advanced improve the speed problem of Reed-Solomon code in coding, and develop an efficient way in the VLSI architecture. Finally we adopt the embedded system of DE2 to develop the co-design coding environment to provide a complete and high reliability scheme.

A new decoder for binary quadratic residue code with irreducible generator polynomial

The binary quadratic residue (QR) codes have nice distance property, but they are difficult to decode for the insufficient consecutive syndromes. The author used the Lagrange interpolation formula to calculate the needed primary unknown syndrome for the binary QR code. In this paper, we propose an efficient hardware architecture to implement this method, and decode the binary QR code by using the well-developed Berlekamp-Massey algorithm and Chien search.

Another Look at the Sequential Multiplier over Normal Bases

The Massey-Omura multiplier is a well-known sequential multiplier over finite fields GF(2m), which can perform multiplication in m clock cycles for the normal basis. In this article, the authors propose a new architecture to carry out the sequential multiplier using normal basis. The time complexity in each cycle of this new multiplier is O(1) and the number of inputs is lower down to m+1, instead of 2m, which is the number needed for most previous multipliers. These merits make it easier to the VLSI implementation