Ming-Hsiang Cho

A novel cascade-based de-embedding method for on-wafer microwave characterization and automatic measurement

This paper presents a general S-parameter de-embedding method using only one OPEN and one THRU dummy structures for on-wafer microwave characterization and automatic measurement. By aggressively combining the transmission-line theory and cascade-configuration concept, this method can efficiently create the scalable and repeatable interconnect parameters to accurately eliminate the redundant parasitics of the device-under-test (DUT). With the application of the proposed technique, both active and passive devices, such as MOSFET, BJT, spiral inductor, and MIM capacitor, can be de-embedded to acquire their intrinsic performances, and the consumption of chip area for on-wafer device characterization can be significantly saved.

A scalable noise de-embedding technique for on-wafer microwave device characterization

In this letter, we present a scalable and efficient noise de-embedding procedure, which is based on transmission-line theory and cascade configurations, for on-wafer microwave measurements of silicon MOSFETs. The proposed de-embedding procedure utilizes one open and one thru dummy structures to eliminate the parasitic effects from the probe pads and the input/output interconnects of a device-under-test (DUT), respectively. This method can generate the scalable distributed interconnect parameters to efficiently and precisely remove the redundant parasitics of the DUTs with various device sizes and arbitrary interconnect dimensions.

Comments on "A shield-based three-port de-embedding method for microwave on-wafer characterization of deep-submicrometer silicon MOSFETs"

A general three-port S-parameter de-embedding method using shield-based test structures for microwave on-wafer characterization is presented in this paper. This method does not require any physical equivalent-circuit assumption for the surrounding parasitics of a device-under-test. We use one open and three thru dummy devices to remove the parasitic components connected to the gate, drain, and source terminals of a MOSFET. By shielding the lossy silicon substrate, the cross-coupling from port to port can be significantly mitigated, and thus, the parasitics of probe pads and interconnects at each port can be separately subtracted. The MOS transistor and its corresponding dummy structures fabricated in a 0.18-/spl mu/m CMOS process were characterized up to 20 GHz. Compared with the two-port cascade-based de-embedding method, the proposed three-port de-embedding procedure can further eliminate the parasitics associated with the dangling leg in the source terminal. The impacts of the accuracy of the de-embedding technique on device modeling and simulation are also discussed.

Unified parasitic de-embedding methodology of on-wafer multi-port device characterization

Systematic de-embedding methodology is proposed for on-wafer characterization of multi-port devices in the RF/microwave regime. This approach incorporates the shield-based measurement technique with the concept of scalable interconnect parameters from transmission-line theory. By grounding the metal shield, the port-to-port coupling and substrate leakage can be substantially mitigated and thus the de-embedding procedure can be simplified. We introduce the open and through dummy structures to eliminate the parasitics associated with the probe pads and interconnects. The four-port spiral transformer and its corresponding dummies were characterized up to 20 GHz, and the influences of the de-embedding accuracy on device characteristics were also demonstrated.

Scalable Short-Open-Interconnect S-Parameter De-Embedding Method for On-Wafer Microwave Characterization of Silicon MOSFETs

In this paper, we propose an accurate and scalable S-parameter de-embedding method for RF/microwave on-wafer characterization of silicon MOSFETs. Based on cascade configurations, this method utilizes planar open, short, and thru standards to estimate the effects of surrounding parasitic networks on a MOS transistor. The bulk-shielded open and short standards are used to simulate and de-embed the probe-pad parasitics. The thru standard are used to extract the interconnect parameters for subtracting the interconnect parasitics in gate and drain terminals of the MOSFET. To further eliminate the parasitics of dangling leg in source terminal of the MOSFET, we also introduce the microwave and multi-port network analysis to accomplish the two-port-to-three-port transformation for S -parameters. The MOSFET and its corresponding de-embedding standards were fabricated in a standard CMOS process and characterized up to 40GHz. The scalability of the open, short, and thru standards is demonstrated and the performance of the proposed de-embedding procedure is validated by comparison with several de-embedding techniques.

Temperature effect on power characteristics of SiGe HBTs

In this paper, the linear power gain, gain expansion and gain compression of power SiGe HBTs at various temperatures have been presented. At low base voltage, the linear power gain increases with increasing temperature, while the linear power gain decreases at high base voltage. Besides we observe the gain expansion will exist as base voltage is in low value, but it will disappear when the temperature increases to 75/spl deg/C. After gain compression, the power gain increases with increasing temperature no matter what the base voltage is. We explain this phenomenon by analyzing the cutoff frequency and the collector current at different temperatures.