Hua-Chou Tseng

Comments on "A shield-based three-port de-embedding method for microwave on-wafer characterization of deep-submicrometer silicon MOSFETs"

A general three-port S-parameter de-embedding method using shield-based test structures for microwave on-wafer characterization is presented in this paper. This method does not require any physical equivalent-circuit assumption for the surrounding parasitics of a device-under-test. We use one open and three thru dummy devices to remove the parasitic components connected to the gate, drain, and source terminals of a MOSFET. By shielding the lossy silicon substrate, the cross-coupling from port to port can be significantly mitigated, and thus, the parasitics of probe pads and interconnects at each port can be separately subtracted. The MOS transistor and its corresponding dummy structures fabricated in a 0.18-/spl mu/m CMOS process were characterized up to 20 GHz. Compared with the two-port cascade-based de-embedding method, the proposed three-port de-embedding procedure can further eliminate the parasitics associated with the dangling leg in the source terminal. The impacts of the accuracy of the de-embedding technique on device modeling and simulation are also discussed.

psub guard ring design and modeling for the purpose of substrate noise isolation in the SOC era

This letter reports the effect of using a p-minus substrate guard ring (psub GR) structure to reduce substrate noise coupling. A corresponding equivalent lump circuit model that predicts the substrate noise isolation behavior of this structure versus distance is also presented. For this particular study, it was found that integrating the psub GR into conventional GR designs can improve substrate noise isolation capabilities of conventional p+ guard rings and n-well guard rings by -15 dB and -5 dB, respectively. This scheme requires no extra masks or processes, and no special substrate material.

Study of nickel silicide contact on Si/Si 1-x Ge x

The properties of nickel silicide formed by depositing nickel on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer are compared with that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer formed by depositing Ni directly on p/sup +/-Si/sub 1-x/Ge/sub x/ layer without silicon consuming layer. After thermal annealing, nickel silicide on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer shows lower sheet resistance and specific contact resistivity than that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer. In addition, small junction leakage current is also observed for nickel silicide on a Si/p/sup +/-Si/sub 1-x/Ge/sub x//n-Si diode. In summary, with a Si consuming layer on top of the Si/sub 1-x/Ge/sub x/, the nickel silicide contact formed demonstrated improved electrical and materials characteristics as compared with the nickel germanosilicide contact which was formed directly on the Si/sub 1-x/Ge/sub x/ layer.

Extraction of substrate parameters for RF MOSFETs based on four-port measurement

In this work, a new method for extracting substrate parameters of radio frequency (RF) metal oxide semiconductor field effect transistors (MOSFETs) based on four-port measurement is presented. A T-liked substrate resistance network is used and the values of all components in the cold MOSFETs were extracted directly from the four-port data between 250 MHz and 8.5 GHz. The output admittance Y/sub 22/ can be well modeled up to 26.5 GHz based on the extracted substrate resistances and the other extrinsic capacitances extracted from an active device.

Linearity and power characteristics of SiGe HBTs at high temperatures for RF applications

In this paper, the power gain, power-added efficiency (PAE) and linearity of power SiGe heterojunction-bipolar transistors at various temperatures have been presented. The power characteristics were measured using a two-tone load-pull system. For transistors biased with fixed base voltage, the small-signal power gain and PAE of the devices increase with increasing temperature at low base voltages, while they decrease at high base voltages. Besides, the linearity is improved at high temperature for all voltage biases. However, for devices with fixed collector current, the small-signal power gain, PAE, and linearity are nearly unchanged with temperature. The temperature dependence of power and linearity characteristics can be understood by analyzing the cutoff frequency, the collector current, Kirk effect and nonlinearities of transconductance at different temperatures.

Hot-carrier induced degradations on RF power characteristics of SiGe heterojunction bipolar transistors

Hot-carrier (HC) effects on high-frequency and RF power characteristics of Si/SiGe HBTs are investigated in this paper. By using the two-tone load-pull measurement, we find that not only the cutoff frequency, but also the output power performances of Si/SiGe HBTs are suffered by the HC stress. In this work, S-parameters and intrinsic elements of an equivalent hybrid-/spl pi/ model were used to validate the HC effects on high-frequency characteristics. With different bias conditions, the degradations of cutoff frequency, power gain, and linearity are found to be worse under constant base-current measurement than that under constant collector-current measurement. The HC-induced degradations on the current gain, transconductance, and ideality-factor of base and collector currents are analyzed to explain the experimental observations.

Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors

A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (/spl les/550/spl deg/C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHV/CVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH/sub 3/ plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step is not needed. A field effect mobility of 46 cm/sup 2//V-s, ON/OFF current ratio of over 10/sup 7/, and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate.

Impact of hot carrier stress on RF power characteristics of MOSFETs

This paper investigates hot-carrier (HC) effects on the RF power and linearity characteristics of MOS transistors using load-pull measurement. We found that the RF power characteristics are affected by the HC stress, and the linearity of MOS transistors is clearly degraded after HC stress at constant gate voltage measurement. However, at high gate voltage bias, the HC-induced power degradation is much reduced compared with that under low gate voltage regimes. In addition, HC effects on linearity can be softened by biasing the transistor at constant drain currents. These experimental observations can be explained by the change of threshold voltage, transconductance, subthreshold swing, and mobility degradation coefficient under HC stress.

Effects of Isolation Oxides on Undercut Formation and Electrical Characteristics for Silicon Selective Epitaxial Growth

Three isolation oxide structures have been prepared to study their resistance to the undercut formation during selective epitaxial growth (SEG) processes. The N 2 O annealed oxide tetraethyoxysilane (TEOS) oxide stacked structure has the best resistance to the undercut formation and exhibits the best electrical characteristics compared to the other two isolation oxide structures prepared in the study, which are a wet oxide and a TEOS oxide. This is ascribed to a smaller interfacial stress between the isolation oxide and the silicon substrate for the stacked structure. The sidewall damage is the predominant factor deteriorating the current-voltage (I-V) characteristics of the N + -P SEG diodes. When treated with a quick HF dip and followed by a low temperature desorption cleaning before the SEG process, the N + -P SEG diode, which has no perceivable undercut, shows satisfactory I-V characteristics.

Slow-wave characteristics of interconnects on silicon substrates

This paper deals with slow-wave characteristics of interconnects on silicon substrates. In slow-wave mechanism, the microstrip lines with and without bottom-shielded ground structures (MIM structures and MIS structures) are characterized. Slow wave propagation in MIS structure occurs when the operation frequency is not so high and the substrate resistivity is moderate, effective permittivity increases and the propagation velocity slows down due to Maxwell-Wagner mechanism. The transmission line parameters such as series resistances and inductances are calculated as the function of frequency. Results shows that the silicon substrate of the non-shielded transmission line can be treated as imperfect ground plane and called as skin-effect mode.