Ming-Kun Chen

Hardware Implementation of RFID Mutual Authentication Protocol

Radio-frequency identification (RFID) is a wireless technology that utilizes radio communication to identify objects with a unique electrical identity. The widespread deployment of RFID technologies may generate new threats to security and user privacy. One of the main drawbacks of RFID technology is the weak authentication systems between a reader and a tag. In general, ¿weak¿ authentication systems that either leak the password directly over the network or leak sufficient information while performing authentication allow intruders to deduce or guess the password. In this paper, we study the RFID tag-reader mutual authentication scheme. A hardware implementation of the mutual authentication protocol for the RFID system is proposed. The proposed system was simulated using Modelsim XE II and synthesized using Xilinx synthesis technology. The system has been successfully implemented in hardware using an Altera DE2 board that included an Altera Cyclone II field-programmable gate array (FPGA). Finally, the output waveforms from the FPGA were displayed on the 16702A logic analysis system for real-time verification.

Design of patch antenna for RFID reader applications

In this paper a single feed circularly polarized patch antenna and a constructed prototype ideal for Gen2 RFID (Generation 2 of Radio frequency identification) reader applications is present. The proposed patch antenna has a simple structure, it have corner truncated square patch, ground plane and a feed line with L-shaped of ground coupled. Through a via hole in the vertical ground of the ground plane, the radiating patch is easily excited by an L-shaped coupled feed oriented in the same plane as the patch, and circular polarization (CP) radiation is achieved. Experimental results of a constructed prototype with the center operating frequency at about 922 MHz showed that the patch antenna has an impedance bandwidth (1.5 ∶ 1 VSWR) of about 10%, return loss S11 of about −26dB and a gain level of 8.5 dB. In addition to the proposed patch antenna due to its simple structure, the obtained CP performance with low cost is among the best that have been reported for single-feed single-element patch antennas.

Study of contact degradation in final testing for BGA socket

BGA socket is most important part in the final testing which selects the good or bad chip of BGA packages. When testing BGA-type packages using a BGA socket, the characteristic contact conditions and mechanisms of surface degradation in a low and stable contact are essential. However, the electrical contact between the pogo pin and the solder ball of the BGA-type package becomes unstable following repeated touchdown operations since particles from the package outline gradually accumulate on the crown tip of pogo pin. The contamination caused by these particles causes the contact resistance to increase. Accordingly, this study develops an experimental procedure for investigating the effect of the particle contamination on the magnitude and stability of the contact resistance. Initially, an experiment is performed to establish the contact resistance between a plated beryllium-copper (BeCu) pin at various number of touchdown. Subsequently, an experiment is conducted to investigate the accumulation of surface particles on the crown tip following multiple touchdowns of the pogo pin with the surface solder ball. The worn-out of crown tip following 6,830 and 36,580 touchdowns, respectively, is examined using a scanning electron microscope (SEM). The experimental results are then integrated to establish a suitable tradeoff between the contact resistance and the number of contacts for the time of socket clean.

Fabrication and characterization of low-cost ultrathin flexible polyimide interposer

Abstract A passive interposer, which is a way to bridge the feature gap between the integrated circuit (IC) and the package substrate, is a key building block for high performance 3-D systems. In this paper, polyimide (PI) is proposed as an alternative to glass and silicon based interposers for cost-effective 2.5-D/3-D IC integration. The development of interconnect technology using an ultrathin flexible polyimide interposer (UFPI) for 2.5-D/3-D packaging applications is described in detail. A semi-additive process consisting of copper seed layer deposition, photolithography, and electrolytic copper pattern plating is used for fabricating a double-sided flexible fan out interposer. A UFPI with electrodeposited micro-scale copper (Cu) fine patterns and laser drilling microvia is investigated using a scanning electron microscope (SEM), energy-dispersive spectrometry (EDS), X-ray spectrometry, and an optical 3-D profilometer. The UFPI with fine pitch on 12.5xa0μm thin PI substrates has been demonstrated. The result is a proof-of-concept to exploit the opportunities of cost-effective 2.5D flexible interposer production.

Failure analysis of Cu electroplating process with Polyimide substrate fabricated for flexible packaging

Failures like short circuit are always encountered in PCBs (printed circuit boards) due to defects in the flexible interconnection. In this paper, systematic analysis such as macro and micro observation was carried out on shorting trace in Polyimides (PI) films used for flexible substrates interconnection (FSI) packaging applications. The thin flexible PI films have desirable properties for use in the electrical and electronics industry because they are a group of good thermal stability, high flexibility, low dielectric constants, excellent mechanical strength, low loss tangent and electrical insulating properties. Since, they offer so many excellent characteristics, this enables a wide range of applications, particularly for flexible packaging. The fine traces with 50 μm pitch (25 μm line/space) built on a flexible 12.5 μm thick polyimide film using wet fabrication process are reported in this paper. The thick copper (Cu) film was obtained from the Cu plating process using evaporated thin film of Cu as the adhesion layer. The fabricated fine-pitch test vehicles are the failure analysis using scanning electron microscope (SEM), energy-dispersive spectrometry (EDS) and X-ray spectrometry technologies.

Planar antennas on flexible substrate for wireless applications

Flex-circuits are a reliable alternative to conventional electronic products. It can offer the same advantages of a printed circuit board: repeatability, reliability, and high density. The design of a planar antenna on a flexible substrate can effectively supersede that of an antenna on a FR-4 substrate for more flexible applications on wireless system integration, such as RFID or Bluetooth link as well as in steering microwave beam.

Electrical Modeling and Circuit Simulation for SI Analysis of High-Speed FC-BGA

The presence of discontinuities along a package interconnection distorts the electromagnetic field pattern, resulting in signal integrity (SI) effects especially at more than 1 Gb/s. Such effects also frequently arise when geometrical and material parameters of components in packages were unexpectedly changed during the assembly process. It may therefore lead to a degradation of the package performance. In this paper, we examine the parasitic effects of signal and power on the high-speed flip-chip ball grid array (FC-BGA) packages. A proposed model is established based on the measurement results. The circuit simulation of the package model can then be performed to analyze the various factors of signal quality.

Failure analysis of EOS-induced damage at final electrical testing

AbstractnThe performance and productivity of microelectronics has increased continuously over more than four decades due to enormous advances in photolithography, wafer size, process technology, and devices. Historically, electrical overstress (EOS) has been one of the leading causes of integrated circuit failures. In this paper, the failure sites are observed on an antiparallel diode string within a power cut cell of a 130xa0nm complementary metal oxide semiconductor mix-signal chip during testing. It was found that the diode string was driven with a forward biased pulse during the power-up and power-down conditions. The slow rise time of the energy pulse indicates that the electrical failure is associated with an EOS event. Failures are verified using scanning electronic microscopy, photoemission microscopy, and liquid crystal analysis. The cause of the failure is either the supply voltage or a timing error in the final testing of the devices.

Co-simulation of capacitive coupling pads assignment for capacitive coupling interconnection applications

Three dimensions packaging provides a very promising technology for the effective integration of complex systems: devices that are optimally implemented with various different technologies can be separately manufactured and then stacked and connected by means of efficient vertical interconnections over a very short range; this provides most of the benefits of inter-chips for high-bandwidth with a reasonable cost and short development time in the advance of CMOS processes and assembly. This study presents the co-simulation of capacitive coupling pads assignment for the capacitive coupling interconnection. The modelling of a close capacitive coupling interconnection pad is represented by a lumped circuit. The coupling pads of parasitic capacitance are one of the parasitic parameters. The FEM (finite element method) tools simulation results show that the effect of cross-coupling between adjacent channels is dependent on substrate characteristic and pads arrangement. A comparison between simulated and measured circuit performance was shown for a RLC-elements, and qualitative accuracy was obtained. HSPICE tools are applied for the circuit simulations using the equivalent model of coupling pads. Based on the findings of this work, co-simulation methods can reduce simulation time dramatically, the coupling pads assignment can be translated to HSPICE model.

Implementation and application of UHF RFID antenna

The implementation of UHF RFID antenna and a testing system is demonstrated in this paper. Four different tags placed in the vicinity of the antenna at different distance and direction to detect the characteristics of the antenna. The experimental results indicate the antenna can cover the existing NCC 922-928MHz band. In addition, the system can be further explored for the application of a location sensing prototype system.