Yu-Jung Huang

Reliability and routability consideration for MCM placement

Abstract This paper presents a methodology based on the fuzzy logic approach for the placement of the power dissipating chips on the multichip module substrate. Our methodology considers both thermal distribution and routing length constraints during multichip module placement. In this paper, the main design issue is the coupled placement for reliability and routability. The objective of the coupled placement is to enhance the system performance and reliability by obtaining an optimal cost during multichip module placement. For reliability considerations, the design methodology is addressed on the placement of the power dissipating chips to achieve uniform thermal distribution. The thermal placement analysis is based on the modified fuzzy force-directed placement method. Placement for routability is based on minimizing the total wire length estimated by semi-perimeter method. The placement trade-off between routability and reliability is illustrated by varying a weighting factor. Case studies of the coupled placement are presented. In addition, the thermal distribution of the coupled placement results is simulated with the finite element method.

Fuzzy thermal modeling for MCM placement

This paper introduces a fuzzy analytical model for the optimal component placement of the power dissipating chips on a multichip module substrate. Our methodology considers multiobjective component placement based on thermal reliability as well as routing length criteria. The objective of the coupled placement methodology is to enhance the performance and reliability of the multichip module system by obtaining an optimal cost during multichip module placement. Case studies of the coupled placement are presented. In addition, the thermal distribution of the coupled placement results is simulated using the finite element method.

Fuzzy logic based thermal design for MCM placement

An algorithm that perform a global placement procedure by taking into account both routability and reliability is presented in this paper. For reliability considerations, the design methodology addresses the placement of the power dissipating chips to achieve a uniform thermal distribution. Placement for routability is based on minimization of the total wire length. The placement trade-offs between routing and reliability are investigated. Our approach to the placement problem is based on the modified force-directed placement method. The proposed thermal force-directed placement method relates the force equations to the power dissipation values of the individual bare chips. Examples of multichip placement are presented. The finite element simulation results show that our approach can obtain better a thermal distribution than other traditional placement methods.

Fabrication and characterization of low-cost ultrathin flexible polyimide interposer

Abstract A passive interposer, which is a way to bridge the feature gap between the integrated circuit (IC) and the package substrate, is a key building block for high performance 3-D systems. In this paper, polyimide (PI) is proposed as an alternative to glass and silicon based interposers for cost-effective 2.5-D/3-D IC integration. The development of interconnect technology using an ultrathin flexible polyimide interposer (UFPI) for 2.5-D/3-D packaging applications is described in detail. A semi-additive process consisting of copper seed layer deposition, photolithography, and electrolytic copper pattern plating is used for fabricating a double-sided flexible fan out interposer. A UFPI with electrodeposited micro-scale copper (Cu) fine patterns and laser drilling microvia is investigated using a scanning electron microscope (SEM), energy-dispersive spectrometry (EDS), X-ray spectrometry, and an optical 3-D profilometer. The UFPI with fine pitch on 12.5xa0μm thin PI substrates has been demonstrated. The result is a proof-of-concept to exploit the opportunities of cost-effective 2.5D flexible interposer production.

Failure analysis of Cu electroplating process with Polyimide substrate fabricated for flexible packaging

Failures like short circuit are always encountered in PCBs (printed circuit boards) due to defects in the flexible interconnection. In this paper, systematic analysis such as macro and micro observation was carried out on shorting trace in Polyimides (PI) films used for flexible substrates interconnection (FSI) packaging applications. The thin flexible PI films have desirable properties for use in the electrical and electronics industry because they are a group of good thermal stability, high flexibility, low dielectric constants, excellent mechanical strength, low loss tangent and electrical insulating properties. Since, they offer so many excellent characteristics, this enables a wide range of applications, particularly for flexible packaging. The fine traces with 50 μm pitch (25 μm line/space) built on a flexible 12.5 μm thick polyimide film using wet fabrication process are reported in this paper. The thick copper (Cu) film was obtained from the Cu plating process using evaporated thin film of Cu as the adhesion layer. The fabricated fine-pitch test vehicles are the failure analysis using scanning electron microscope (SEM), energy-dispersive spectrometry (EDS) and X-ray spectrometry technologies.

Fabrication and characterization of ultrathin fine-pitch flexible polyimide interposer

A three-dimensional system-in-package (3-D SiP) based on silicon carriers or an interposer is a fast-emerging technology that offers system design flexibility and the integration of heterogeneous technologies. A passive interposer, which is a way to bridge the feature gap between the integrated circuit (IC) and the package substrate, is a key building block for high performance 3-D systems. The need for high-density interconnection to support 3-D integration has led to a growing demand for the development of fine-pitch and small vias on the interposer. Polyimide base films have been used extensively for flexible and high-density electronic interconnection applications because they offer good thermal and chemical stability with a lower dielectric constant. In this paper, the development of interconnect technology using an ultrathin flexible polyimide interposer (UFPI) for 2.5-D/3-D packaging applications is described in detail. A UFPI with electrodeposited micro-scale copper (Cu) fine patterns (≤50 μm) and laser drilling microvia is investigated using a scanning electron microscope (SEM), energy-dispersive spectrometry (EDS), X-ray spectrometry, and an optical 3-D profilometer. The UFPI can be used to support the very high I/O, high-performance, high-density, and fine-pitch ultrathin chips packages.

Fabrication of fine pitch copper patterns on flexible substrate

In order to fabricate flexible microelectronic devices, fabrication of metallization lines and metal electrodes on the flexible substrate is essential. For minimizing the size of device, the realization of metallization lines with the scale of a few micrometers on the flexible substrate is very important. In this study, pulse electroplating has been applied in order to metalize PI surfaces with Cu. The micro-scale fine patterns Cu metallization processes on PI substrate are described.

Failure analysis of EOS-induced damage at final electrical testing

AbstractnThe performance and productivity of microelectronics has increased continuously over more than four decades due to enormous advances in photolithography, wafer size, process technology, and devices. Historically, electrical overstress (EOS) has been one of the leading causes of integrated circuit failures. In this paper, the failure sites are observed on an antiparallel diode string within a power cut cell of a 130xa0nm complementary metal oxide semiconductor mix-signal chip during testing. It was found that the diode string was driven with a forward biased pulse during the power-up and power-down conditions. The slow rise time of the energy pulse indicates that the electrical failure is associated with an EOS event. Failures are verified using scanning electronic microscopy, photoemission microscopy, and liquid crystal analysis. The cause of the failure is either the supply voltage or a timing error in the final testing of the devices.

Design of AC-coupled circuit for high-speed interconnects

The scaling of semiconductor technology together with 3D IC stacking integration make it possible for many portable electronics to process large amount of multimedia data. AC-coupling enables chip placed face-to-face for signal transmission using close-field capacitive coupling. A high performance system design using AC coupled interconnect (ACCI) technology not only achieves shorter and faster interconnection between dies but also increases packaging density. This paper describes a chip-to-chip circuit design suitable for high-speed 3DIC interconnected applications. The AC-Coupled face-to-face (F2F) chip was simulated using HSPICE with TSMC 0.18-μm 1P6M CMOS technology process file under a 1.8 V supply voltage. The simulation results indicated the proposed circuit with the self-test characteristics can achieve differential signal transmission up to 2.5 Gbps.

Micro-scale Cu metallization on polyimide substrate for high-speed interconnects

The present study can be applicable to fine wire interconnections, particularly for high-speed solutions in 3D packaging. The fine traces with 50 micron pitch (25 ¼m line/space) built on a flexible 50 micron thick polyimide film using wet fabrication process are reported in this paper. The thick copper (Cu) layer was obtained from the Cu plating process using evaporated ultra-thin layer of Cu as the adhesion layer between Cu and a Polyimide (PI). The fabricated fine-pitch pattern is inspected for further failure analysis using scanning electron microscope (SEM) and energy-dispersive spectrometry (EDS) technologies. The experiment is conducted to study the effect of the process parameters on the Cu film surface properties. The results obtained in this work can be applied to the fabrication of flexible high-speed interconnection devices.