Minsik Cho

A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips

In this paper, we propose a high-performance droplet router for a digital microfluidic biochip (DMFB) design. Due to recent advancements in the biomicro electromechanical system and its various applications to clinical, environmental, and military operations, the design complexity and the scale of a DMFB are expected to explode in the near future, thus requiring strong support from CAD as in conventional VLSI design. Among the multiple design stages of a DMFB, droplet routing, which schedules the movement of each droplet in a time-multiplexed manner, is one of the most critical design challenges due to high complexity as well as large impacts on performance. Our algorithm first routes a droplet with higher by passibility which is less likely to block the movement of the others. When multiple droplets form a deadlock, our algorithm resolves it by backing off some droplets for concession. The final compaction step further enhances timing as well as fault tolerance by tuning each droplet movement greedily. The experimental results on hard benchmarks show that our algorithm achieves over 35 x and 20 x better routability with comparable timing and fault tolerance than the popular prioritized A* search and the state-of-the-art network-flow-based algorithm, respectively.

BoxRouter 2.0: architecture and implementation of a hybrid and robust global router

In this paper, we present BoxRouter 2.0, a hybrid and robust global router with discussion on its architecture and implementation. As high performance VLSI design becomes more interconnect-dominant, efficient congestion elimination in global routing is in greater demand. Hence, we propose BoxRouter 2.0 which has strong ability to improve routability and minimize the number of vias with blockages, while minimizing wirelength. BoxRouter 2.0 is improved over [1], but can perform multi-layer routing with 2D global routing and layer assignment. Our 2D global routing is equipped with two ideas: robust negotiation-based A* search for routing stability, and topology-aware wire ripup for flexibility. After 2D global routing, 2D-to-3D mapping is done by the layer assignment which is powered by progressive via/blockage-aware integer linear programming. Experimental results show that BoxRouter 2.0 has better routability with comparable wirelength than other routers on ISPD07 benchmark, and it can complete (no overflow) ISPD98 benchmark for the first time in the literature with the shortest wirelength.

Double patterning technology friendly detailed routing

Double patterning technology (DPT) is a most likely lithography solution for 32/22 nm technology nodes as of 2008 due to the delay of extreme ultra violet lithography. However, it should hurdle two challenges before being introduced to mass production, layout decomposition and overlay error. In this paper, we present the first detailed routing algorithm for DPT to improve layout decomposability and robustness against overlay error, by minimizing indecomposable wirelength and the number of stitches. Experimental results show that the proposed approach improves the quality of layout significantly in terms of decomposability and the number of stitches with 3.6x speedup, compared with a current industrial DPT design flow.

A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography

As Double Patterning Lithography(DPL) becomes the leading candidate for sub-30nm lithography process, we need a fast and lithography friendly decomposition framework. In this paper, we propose a multi-objective min-cut based decomposition framework for stitch minimization, balanced density, and overlay compensation, simultaneously. The key challenge of DPL is to accomplish high quality decomposition for large-scale layouts under reasonable runtime with the following objectives: a) the number of stitches is minimized, b) the balance between two decomposed layers is maximized for further enhanced patterning, c) the impact of overlay on coupling capacitance is reduced for less timing variation. We use a graph theoretic algorithm for minimum stitch insertion and balanced density. An additional decomposition constraints for self-overlay compensation are obtained by integer linear programming(ILP). With the constraints, global decomposition is executed by our modified FM graph partitioning algorithm. Experimental results show that the proposed framework is highly scalable and fast: we can decompose all 15 benchmark circuits in five minutes in a density balanced fashion, while an ILP-based approach can finish only the smallest five circuits. In addition, we can remove more than 95% of the timing variation induced by overlay for tested structures.

BoxRouter: a new global router based on box expansion and progressive ILP

In this paper, we propose a new global router, BoxRouter, powered by the concept of box expansion, progressive integer linear programming (PILP), and adaptive maze routing (AMR). BoxRouter first uses a simple prerouting strategy to predict and capture the most congested region with high fidelity as compared to the final routing. Based on progressive box expansion initiated from the most congested region, BoxRouting is performed with PILP and AMR. Our PILP is shown to be much more efficient than the traditional ILP in terms of speed and quality, and the AMR based on multisource multitarget with bridge model is effective in minimizing the congestion and wirelength. It is followed by an effective postrouting step, which reroutes without rip-up to enhance the routing solution further and obtain smooth tradeoff between wirelength and routability. Our experimental results show that the BoxRouter significantly outperforms the state-of-the-art published global routers, e.g., 91 % better routability than Labyrinth (with 14% less wirelength and 3.3times speedup), 79% better routability than Chi-dispersion router (with similar wirelength and 2times speedup), and 4.2% less wirelength and 16times speedup than a multicommodity flow-based router (with similar routability). Additional enhancement in box expansion and postrouting further improves the result with similar wirelength but much better routability than the latest work in global routing.

Wire density driven global routing for CMP variation and timing

In this paper, we propose the first wire density driven global routing that considers CMP variation and timing. To enable CMP awareness during global routing, we propose a compact predictive CMP model with dummy fill, and validate it with extensive industry data. While wire density has some correlation and similarity to the conventional congestion metric, they are indeed different in the global routing context. Therefore, wire density rather than congestion should be a unified metric to improve both CMP variation and timing. The proposed wire density driven global routing is implemented in a congestion-driven global router (M. Cho and D. Z. Pan, 2006) for CMP and timing optimization. The new global router utilizes several novel techniques to reduce the wire density of CMP and timing hotspots. Our experimental results are very encouraging. The proposed algorithm improves CMP variation and timing by over 7% with negligible overhead in wirelength and even slightly better routability, compared to the pure congestion-driven global router (M. Cho and D. Z. Pan, 2006)

TACO: temperature aware clock-tree optimization

In this paper, an efficient linear time algorithm TACO is proposed for the first time to minimize the worst case clock skew in the presence of on-chip thermal variation. TACO, while tries to minimize the worst case clock skew, also attempts to minimize the clock tree wirelength by building up merging diamonds in a bottom-up manner. As an output, TACO provides balanced merging points and the modified clock routing paths to minimize the worst case clock skew under thermal variation. Experimental results on a set of standard benchmarks show 50-70% skew reduction with less than 0.6% wirelength overhead.

BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability

In this article, we present BoxRouter 2.0, and discuss its architecture and implementation. As high-performance VLSI design becomes more interconnect-dominant, efficient congestion elimination in global routing is in greater demand. Hence, we propose a global router which has a strong ability to improve routability and minimize the number of vias with blockages, while minimizing wirelength. BoxRouter 2.0 is extended from BoxRouter 1.0, but can perform multi-layer routing with 2D global routing and layer assignment. Our 2D global routing is equipped with two ideas: node shifting for congestion-aware Steiner tree and robust negotiation-based A* search for routing stability. After 2D global routing, 2D-to-3D mapping is done by the layer assignment which is powered by progressive via/blockage-aware integer linear programming. Experimental results show that BoxRouter 2.0 has better routability with comparable wirelength than other routers on ISPD07 benchmark, and it can complete (no overflow) the widely used ISPD98 benchmark for the first time in the literature with the shortest wirelength. We further generate a set of harder ISPD98 benchmarks to push the limit of BoxRouter 2.0, and propose the hardened ISPD98 benchmarks to map state-of-the-art solutions for future routing research.

Optimal layout decomposition for double patterning technology

Double patterning technology (DPT) is regarded as the most practical solution for the sub-22nm lithography technology. DPT decomposes a single layout into two masks and applies double exposure to print the shapes in the layout. DPT requires accurate overlay control. Thus, the primary objective in DPT decomposition is to minimize the number of stitches (overlay) between the shapes in the two masks. The problem of minimizing the number of stitches in DPT decomposition is conjectured to be NP-hard. Existing approaches either apply Integer Linear Programming (ILP) or use heuristics. In this paper, we show that the problem is actually in P and present a method to decompose a layout for DPT and minimize the number of stitches optimally. The complexity of the method is O(n1.5 log n). Experimental results show that the method is even faster than the fast heuristics.

A high-performance droplet router for digital microfluidic biochips

In this paper, we propose a high-performance droplet router for digital microfluidic biochip (DMFB) design. Due to recent advancements in bio-MEMS, the design complexity and the scale of a DMFB are expected to explode in near future, thus requiring strong support from CAD as in conventional VLSI design. Among multiple design stages of a DMFB, droplet routing which schedules the movement of each droplet in a time-multiplexed manner is a critical challenge due to high complexity as well as large impacts on performance. Our algorithm first routes a droplet with higher bypassibility which less likely blocks the movement of the others. When multiple droplets form a deadlock, our algorithm resolves it by backing off some droplets for concession. A final compaction step further enhances timing as well as fault-tolerance by tuning each droplet movement greedily. Experimental results on hard benchmarks show that our algorithm achieves over 35x and 20x better routability with comparable timing and fault-tolerance than the popular prioritized A* search [2] and the state-of-the-art network-flow based algorithm [18], respectively