Yongchan Ban

Double patterning technology friendly detailed routing

Double patterning technology (DPT) is a most likely lithography solution for 32/22 nm technology nodes as of 2008 due to the delay of extreme ultra violet lithography. However, it should hurdle two challenges before being introduced to mass production, layout decomposition and overlay error. In this paper, we present the first detailed routing algorithm for DPT to improve layout decomposability and robustness against overlay error, by minimizing indecomposable wirelength and the number of stitches. Experimental results show that the proposed approach improves the quality of layout significantly in terms of decomposability and the number of stitches with 3.6x speedup, compared with a current industrial DPT design flow.

Flexible 2D layout decomposition framework for spacer-type double pattering lithography

A spacer-type self-aligned double pattering (SADP) is a pitch-splitting sidewall image method that is a major option for sub-30nm device node manufacturing due to its lower overlay sensitivity and better process window compared to other double patterning processes, such as litho-etch-litho-etch (LELE). SADP is in production use for 1D patterns in NAND Flash memory applications but applying SADP to 2D random logic patterns is challenging. In this paper, we describe the first layout decomposition methods of SADP lithography for complex 2D layouts. The favored type of SADP for complex logic interconnects is a two mask approach using a core (mandrel) mask and a trim mask. This paper describes methods for automatically choosing and optimizing the manufacturability of base core mask patterns, generating assist core patterns, and optimizing trim mask patterns to accomplish high quality layout decomposition in SADP process. We evaluate our technique on 22nm node industrial standard cells and logic designs. Experimental results show that our proposed layout decomposition for SADP effectively decomposes many challenging 2D layouts.

Electrical impact of line-edge roughness on sub-45-nm node standard cells

Since line-end roughness (LER) has been reported to be of the order of several nanometers and to not decrease as the device shrinks, it has evolved as a critical problem in sub-45-nm devices and may lead to serious device parameter fluctuations and performance limitations for future very large scale integration (VLSI) circuit applications. We present a new cell characterization methodology that uses the nonrectangular gate print images generated by lithography and etch simulations with the random LER variation. We systematically analyze the random LER by taking the impact on circuit performance due to LER variation into consideration. We observed that the saturation current, delay, and leakage current are highly affected by LER as the gate length becomes thinner. Results show that when the root mean square value of LER is 6 nm from its nominal line edge, the worst case saturation current, delay, and leakage current degradation are as much as 10.3% decrease, 12.4% increase, and 7× increase at a 45-nm-node standard cell. Meanwhile the current, delay, and leakage current degradation at a 32-nm-node cell are up to 19.0% decrease, 21.8% increase, and 4600× increase, respectively.

ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction

In this paper, we present ELIAD, an efficient lithography aware detailed router to optimize silicon image after optical proximity correction (OPC) in a correct-by-construction manner. We first propose a compact post-OPC litho-metric for a detailed router based on statistical characterization. We characterize the interferences among weak grids filled with one of predefined litho-prone shapes (e.g., jog-corner, via, line-end). Our litho-metric derived from the characterization shows high fidelity to total edge placement error (EPE) in large scale, compared with Calibre-OPC/ORC. As a chip itself is in the largest scale, ELIAD powered by the proposed metric can enhance the overall post-OPC printed silicon image. Experimental results on 65 nm industrial circuits show that ELIAD outperforms a ripup/rerouting approach such as RADAR [17] with 8times more EPE hotspot reduction and 12times speedup. Also, compared with a conventional detailed router, ELIAD is only about 50% slower.

Layout decomposition of self-aligned double patterning for 2D random logic patterning

Self-aligned double pattering (SADP) has been adapted as a promising solution for sub-30nm technology nodes due to its lower overlay problem and better process tolerance. SADP is in production use for 1D dense patterns with good pitch control such as NAND Flash memory applications, but it is still challenging to apply SADP to 2D random logic patterns. The favored type of SADP for complex logic interconnects is a two mask approach using a core mask and a trim mask. In this paper, we first describe layout decomposition methods of spacer-type double patterning lithography, then report a type of SADP compliant layouts, and finally report SADP applications on Samsung 22nm SRAM layout. For SADP decomposition, we propose several SADP-aware layout coloring algorithms and a method of generating lithography-friendly core mask patterns. Experimental results on 22nm node designs show that our proposed layout decomposition for SADP effectively decomposes any given layouts.

Dealing with IC manufacturability in extreme scaling

As the CMOS feature enters the era of extreme scaling (14nm, 11nm and beyond), manufacturability challenges are exacerbated. The nanopatterning through the 193nm lithography is being pushed to its limit, through double/triple or more general multiple patterning, while non-conventional lithography technologies such as extreme ultra-violet (EUV), e-beam direct-write (EBDW), and so on, still have grand challenges to be solved for their adoption into IC volume production. This tutorial will provide an overview of key overarching issues in nanometer IC design for manufacturability (DFM) with these emerging lithography technologies, from modeling, mask synthesis, to physical design and beyond.

Total sensitivity based dfm optimization of standard library cells

Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. How to design robust cells under variations plays a crucial role in the overall circuit performance and yield. In this paper we propose a comprehensive sensitivity metric which seamlessly incorporates effects from device criticality, lithographic proximity, and process variations. We develop first-order models to compute these sensitivities, and perform robust layout optimization by minimizing the total delay sensitivity to reduce the delay variation on the nominal process condition and by minimizing the performance gap between the fastest and the slowest delay corners to reduce the leakage current on the process corner. The results on industrial 45nm node standard cells show up to 76% improvement in non-rectangular delay variation under nominal process condition, 24% reduction in the delay difference between the fastest and slowest process corners, and up to 90% reduction in leakage current at the fastest process corner.

Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line

As minimum feature size and pitch spacing further decrease in advanced technology nodes, many new design constraints and challenges are introduced, such as regularity, middle of line (MOL) structures, and pin-access challenges. In this work, we propose a comprehensive study on standard cell layout regularity and pin access optimization. Given irregular cell layout from old technology nodes, our cell optimization tool can search unidirectional migrated result where the self-aligned double patterning (SADP) and MOL based design constraints are satisfied, and the pin-accessibility is optimized. This problem is formulated as a general integer linear programming (ILP), which may suffer from long runtime for some large standard cell cases. Therefore, we also develop a set of hybrid techniques to quickly search for high-quality solutions. The experimental results demonstrate the effectiveness of our approaches.

Electrical impact of line-edge roughness on sub-45nm node standard cell

As the transistors are scaled down, undesirable performance mismatch in identically designed transistors increases and hence causes greater impact on circuit performance and yield. Since Line-End Roughness (LER) has been reported to be in the order of several nanometers and not to decrease as the device shrinks, it has evolved as a critical problem in the sub-45nm devices and may lead to serious device parameter fluctuations and performance limitation for the future VLSI circuit application. Although LER is a kind of random variation, it is undesirable and has to be analyzed because it causes the device to fluctuate. In this paper, we present a new cell characterization methodology which uses the non-rectangular gate print-images generated by lithography and etch simulations with the random LER variation to estimate the device performance of a sub-45nm design. The physics based TCAD simulation tool is used for validating the accuracy of our LER model. We systematically analyze the random LER by taking the impact on circuit performance due to LER variation into consideration and suggest the maximum tolerance of LER to minimize the performance degradation. We observed that the driving current is highly affected by LER as the gate length becomes thinner. We performed lithography simulations using 45nm process window to examine the LER impact of the state-of-the-art industrial devices. Results show that the rms value of LER is as much as 10% from its nominal line edge, and the saturation current can vary by as much as 10% in our 2-input NAND cell.

ELIAD: Efficient Lithography Aware Detailed Routing Algorithm With Compact and Macro Post-OPC Printability Prediction

In this paper, we present an efficient lithography aware detailed (ELIAD) router to enhance silicon image after optical proximity correction (OPC) in a correct-by-construction manner. We first quantitatively show that a pre-OPC litho-metric is highly uncorrelated with a post-OPC metric, which stresses the importance of a post-OPC litho-metric for design-time optimization. We then propose a compact post-OPC litho-metric for a detailed router (DR) based on statistical characterization, where the interferences among predefined litho-prone shapes are captured as a lookup table. Our litho-metric derived from the characterization shows high fidelity to the total edge placement error (EPE) in large scale, compared with Calibre OPC/optical rule check. Therefore, ELIAD powered by the proposed litho-metric can enhance the overall post-OPC printed silicon image. Experimental results on 65-nm industrial circuits show that ELIAD outperforms a rip-up/rerouting approach such as Resolution-enhancement-technique-Aware Detailed Routing with 8times more EPE hot spot reduction and 12times speedup. Moreover, compared with a conventional DR, ELIAD is only about 50% slower.