Mirjana Videnovic-Misic

A low power 3.1–7.5 GHz tunable pulse generator for impulse radio UWB

A novel energy-efficient tunable impulse radio ultra wide band (IR-UWB) pulse generator (PG) for the high data rate 3.1-7.5 GHz band applications is proposed. Glitch generator, switched ring oscillator, buffer and pulse shaping filter are the key components. The circuit is scalable both in bandwidth and center frequency. The glitch generator combines falling edge of the input signal and its delayed inverse, allowing the impulse duration to be tuned over a wide range (250-660 ps) by varying the delay between the edges. The generated impulse duration approximately defines the PGs signal width and thus its spectrum bandwidth. The ring oscillator frequency, which determines the spectrum center frequency, is controlled by the gate control voltage of the PMOS transistor used as an inverter feedback in the ring oscillator. Post-layout simulations show the pulse amplitude of 261 mV and the pulse duration around 700 ps. The total power consumption is only 697 μW with a supply voltage of 1.8 V. The PG is designed in UMC 0.18μm CMOS technology with the total chip area of 602×587 μm2.

Effect of fluorination and hydrogenation by ion implantation on reliability of poly-Si TFTs under gamma irradiation

Sputtered thin film transistors (TFTs), which were hydrogenated and fluorinated by ion implantation, were exposed to gamma irradiation up to 2500?Gy. Long term post-irradiation stability of TFTs was studied after eight months of storage and under positive bias test at 150??C in time intervals of 1?10?h. The effects induced by irradiation and during relaxation period were monitored by current?voltage (I?V) measurements. I?V data were used to determine post-irradiation changes in different TFT parameters, such as threshold voltage, interface states density and grain boundaries trap density. The behaviour of these parameters was compared for four types of TFTs: non-fluorinated-hydrogenated, fluorinated, hydrogenated and fluorinated-hydrogenated, and it was found that hydrogenated TFTs showed greater instability. A mechanism for grain boundary traps generation is proposed.

A 2.4 GHz high-gain low noise amplifier

In this work a design of a 2.4 GHz current reuse low noise amplifier (LNA) in a standard 0.35 µm SiGe technology is presented. In order to achieve good input matching for narrow bandwidth the inductive source degeneration LNA topology is used. Low power consumption with higher gain is obtained using current reuse configuration. In order to provide good isolation and stability cascode amplifier, as a part of current reuse topology, is used. For given configuration, good trade-off between low noise, high gain and stability has been achieved. Optimized LNA has −21.18 dB input return loss (S11), high reverse isolation of −47.51 dB (S12), very high voltage gain (S21) of 23.54 dB, −15.93 dB output return loss (S22), noise figure of 2.7 dB, and a power consumption of 5 mA at 3.3 V. The LNA presented offers high circuit stability parameters B1f=979.6 m and K=7.658.

A 3–10 GHz ultra wideband 130 nm CMOS low noise amplifier

An ultra wideband (UWB) low nose amplifier (LNA) is presented in this paper. It is designed to operate in the complete range (3-10 GHz) as defined by the US Federal Communications Commission (FCC) using the 130 nm CMOS technology process. The main goals of the design are low noise, high linearity and low variance of the gain over the operating frequency range. To achieve this, the two stage topology is used that yields the following results: input reffered intercept point (IIP3) of up to 2.30 dBm and forward gain (S21) of 14.73 dB with the variation of ±1.15 dB over the mentioned range. Maximum noise factor (NF) is less than 4 dB and the input return loss (S11) is less than -10 dB. The power dissipation is 32.50 mW for the supply voltage of 1.20 V. The process, voltage and temperature (PVT) variations are analysed and the results are discussed in the paper. The results given are obtained through the schematic level simulations using Spectre Simulator from Cadence Design System.

Performance comparison of standard and voltage controlled ring oscillator for UWB-IR pulse generator in 0.35µm and 0.18µm CMOS technologies

A CMOS standard ring oscillators with 5 and 7 stages are examined in 0.35µm and 0.18µm technologies. For optimum number of ring oscillator stages (N = 5) the operating frequencies of 1.62 GHz and 3.07 GHz are obtained in 0.35µm and 0.18µm technologies, respectively. The 5-stage ring oscillator topology is further investigated while changing power supply and temperature. Their influence on oscillating frequency can be compensated by introducing additional voltage controlled cascade PMOS or/and NMOS transistors in one inverter stage. As ring oscillator is a part of UWB-IR (Ultra Wide Band Impulse Radio) pulse generator, its oscillating frequency determines the central frequency of the pulse spectrum and influence significantly spectrum fitting within UWB FCC mask.

A 0.18μm CMOS low power LNA for 6–8.5 GHz UWB receivers

This paper presents the design of an ultra-wideband (UWB) low noise amplifier (LNA) in 0.18μm CMOS technology. Proper input matching is achieved with inductive degenerated amplifier circuit modified with resistive feedback. To provide good isolation and stability, cascode amplifier, as a first amplifying stage, is used. Additional common source stage is introduced by using current reuse technique. Operated at 1.8 V LNA consumes only 5.26 mW. The simulation results show maximum power gain of 14.3 dB, while the input and output return loss is less than −10 dB, within the bandwidth from 6 to 8.5 GHz. The noise figure of the LNA varies from 3.9 to 6.8 dB.

Basic figures of merit for A 1.575 GHz low noise amplifier in 0.35 µm SiGe BiCMOS technology

A design of 1.575 GHz two-stage low noise amplifier (LNA) in a BiCMOS 0.35 µm process is presented. First LNA stage is common source amplifier in cascode configuration with source degeneration set for input matching. Additional stage is introduced in order to increase S21 of the LNA. Simulation results for S11, S12, S21 and S22, together with NF, Kf and B1f are given for presented LNA topology.

Modelling of Dual-Gate MOSFET 1/f Noise in Linear Region

This paper presents experimental and numerical results for the dual-gate MOSFET (DGMOSFET) normalized 1/f noise parameter B/ID 2 in linear working region. In modelling, gate-to-gate interelectrode space influence is taken into account with the fitting parameter m, which is defined as the ratio of inner transistors channel lengths. Model and methodology for the normalized 1/f noise parameter calculation for the DGMOSFET linear region have been proposed. The model is based on the ac current approach in the DGMOSFET low-frequency small-signal noise equivalent circuit and carrier-number fluctuations and correlated mobility fluctuations. It has been shown that discrepancy between measured data and numerical results obtained only by the DeltaN model can be explained by use of the gradual channel approximation MOSFET model and the unified 1/f noise model.

Compact UWB resistive feedback low noise amplifier utilizing current bleeding technique

In this paper, a low-noise amplifier (LNA) designed for the lower band of the ultra-wideband (UWB) spectrum and implemented in 0.18 μm CMOS process is presented. Post-layout simulations show a power gain (S21) of 11.18 dB with 0.8 dB value variations from 259 MHz to 5 GHz. The input and output return losses, S11 and S22, are below -10 dB from 466.4 MHz to 5.63 GHz, while reverse isolation (S12) is better than -24.44 dB across the whole simulated range, from 100 MHz to 7 GHz. The average value of noise figure (NF) is 4.48 dB, with minimum value of 4.24 dB at 1.37 GHz. The input-referred third-order intercept point (IIP3) and the input-referred 1-dB compression point (P1dB) are -12.72 dBm and -20.9 dBm, respectively. The LNA core area occupies 0.353 mm2 and consumes 11.16 mW from a 1.8 V supply.

A novel low-complexity BPSK IR-UWB pulse generator in 0.13um CMOS technology

A new low-complexity energy-efficient impulse radio ultra-wideband (IR-UWB) pulse generator is investigated in the paper. It is designed and simulated in low-cost 0.13 μm UMC CMOS technology. The spectrum adjustable architecture consists of a tunable glitch generator, a BPSK modulator, two voltage controlled ring oscillators, an output buffer and a shaping filter. The simulation results showed spectrum that covers the higher UWB band and fully complies with the corresponding FCC spectral mask. The pulse duration is around 0.6 ns, and the peak-to-peak amplitude is 380 mV on 50 Ω output load. It has low power consumption of 0.44 mW corresponding to energy consumption of 2.2 pJ per pulse for 200 MHz pulse repetition frequency (PRF).