Jelena Radic

A low power 3.1–7.5 GHz tunable pulse generator for impulse radio UWB

A novel energy-efficient tunable impulse radio ultra wide band (IR-UWB) pulse generator (PG) for the high data rate 3.1-7.5 GHz band applications is proposed. Glitch generator, switched ring oscillator, buffer and pulse shaping filter are the key components. The circuit is scalable both in bandwidth and center frequency. The glitch generator combines falling edge of the input signal and its delayed inverse, allowing the impulse duration to be tuned over a wide range (250-660 ps) by varying the delay between the edges. The generated impulse duration approximately defines the PGs signal width and thus its spectrum bandwidth. The ring oscillator frequency, which determines the spectrum center frequency, is controlled by the gate control voltage of the PMOS transistor used as an inverter feedback in the ring oscillator. Post-layout simulations show the pulse amplitude of 261 mV and the pulse duration around 700 ps. The total power consumption is only 697 μW with a supply voltage of 1.8 V. The PG is designed in UMC 0.18μm CMOS technology with the total chip area of 602×587 μm2.

A 2.4 GHz high-gain low noise amplifier

In this work a design of a 2.4 GHz current reuse low noise amplifier (LNA) in a standard 0.35 µm SiGe technology is presented. In order to achieve good input matching for narrow bandwidth the inductive source degeneration LNA topology is used. Low power consumption with higher gain is obtained using current reuse configuration. In order to provide good isolation and stability cascode amplifier, as a part of current reuse topology, is used. For given configuration, good trade-off between low noise, high gain and stability has been achieved. Optimized LNA has −21.18 dB input return loss (S11), high reverse isolation of −47.51 dB (S12), very high voltage gain (S21) of 23.54 dB, −15.93 dB output return loss (S22), noise figure of 2.7 dB, and a power consumption of 5 mA at 3.3 V. The LNA presented offers high circuit stability parameters B1f=979.6 m and K=7.658.

A 3.1 – 6.65 GHz, 933µW impulse radio pulse generator with tuneable spectrum in 0.18µm CMOS

A low-power tuneable impulse radio ultra wide band (IR-UWB) pulse generator (PG) for 3.1 - 6.65 GHz band applications is proposed. To provide compensation due to process, voltage and temperature (PVT) variations and achievement of best performance, the PG is capable of adjusting the Power Spectral Density (PSD) modifying the generated pulse amplitude and duration. Furthermore, the spectrum center frequency can be tuned by changing the frequency of the voltage controlled ring oscillator. Post-layout simulations show the pulse amplitude of 315 mV and the pulse duration around 1 ns. The generated signal spectrum fully complies with the FCC spectral regulations. The total power consumption is only 933 μW with supply voltage of 1.8 V. This corresponds to energy consumption of 11.67 pJ/pulse for a 80 MHz pulse repetition frequency (PRF). The PG is designed in UMC 0.18μm CMOS process with the total chip area of 0.35 μm2.

Performance comparison of standard and voltage controlled ring oscillator for UWB-IR pulse generator in 0.35µm and 0.18µm CMOS technologies

A CMOS standard ring oscillators with 5 and 7 stages are examined in 0.35µm and 0.18µm technologies. For optimum number of ring oscillator stages (N = 5) the operating frequencies of 1.62 GHz and 3.07 GHz are obtained in 0.35µm and 0.18µm technologies, respectively. The 5-stage ring oscillator topology is further investigated while changing power supply and temperature. Their influence on oscillating frequency can be compensated by introducing additional voltage controlled cascade PMOS or/and NMOS transistors in one inverter stage. As ring oscillator is a part of UWB-IR (Ultra Wide Band Impulse Radio) pulse generator, its oscillating frequency determines the central frequency of the pulse spectrum and influence significantly spectrum fitting within UWB FCC mask.

A 0.18μm CMOS low power LNA for 6–8.5 GHz UWB receivers

This paper presents the design of an ultra-wideband (UWB) low noise amplifier (LNA) in 0.18μm CMOS technology. Proper input matching is achieved with inductive degenerated amplifier circuit modified with resistive feedback. To provide good isolation and stability, cascode amplifier, as a first amplifying stage, is used. Additional common source stage is introduced by using current reuse technique. Operated at 1.8 V LNA consumes only 5.26 mW. The simulation results show maximum power gain of 14.3 dB, while the input and output return loss is less than −10 dB, within the bandwidth from 6 to 8.5 GHz. The noise figure of the LNA varies from 3.9 to 6.8 dB.

Composition of Essential Oils of Flowers, Leaves, Stems and Rhizome of Peucedanum officinale L. (Apiaceae)

Abstract The results of the chemical investigations of the essential oils from the flowers, leaves, stems and rhizome of Peucedanum officinale are presented. The essential oil contents were 1.21% (v/w) in flowers, 0.64% (v/w) in leaves, 0.08% (v/w) in stems and 0.24% (v/w) in rhizome. By GC and GC/MS analysis, in all four oils the total of 132 compounds was identified: 53 constituents (93.4% of total amount) in the oil obtained from the flowers, 70 (94.3% of total amount) in the oil from the leaves, 78 (87.8% of total amount) in the oil from the stems and 67 (95.9% of total amount) in the oil from rhizome. In all oils investigated, monoterpenes were the dominant class of constituents (73.9–83.7%), with hydrocarbons (65.6–81.6%) as the most abundant representatives. Limonene, α-pinene and sabinene were identified as the most important constituents in common for all four oils. In the oil from the flowers, leaves and stems, β-pinene and myrcene were also abundant. However, the flower oil differed from the others by a significant quantity of α-phellandrene.

Digitally controlled attenuator

Wide band digitally controlled attenuator implemented in standard 130nm UMC CMOS process has been presented. Attenuator is composed of four cascade Pi-attenuation cells, and it is designed to achieve constant attenuation step size in a wide frequency range from 3.2 to 9.3 GHz.

Compact UWB resistive feedback low noise amplifier utilizing current bleeding technique

In this paper, a low-noise amplifier (LNA) designed for the lower band of the ultra-wideband (UWB) spectrum and implemented in 0.18 μm CMOS process is presented. Post-layout simulations show a power gain (S21) of 11.18 dB with 0.8 dB value variations from 259 MHz to 5 GHz. The input and output return losses, S11 and S22, are below -10 dB from 466.4 MHz to 5.63 GHz, while reverse isolation (S12) is better than -24.44 dB across the whole simulated range, from 100 MHz to 7 GHz. The average value of noise figure (NF) is 4.48 dB, with minimum value of 4.24 dB at 1.37 GHz. The input-referred third-order intercept point (IIP3) and the input-referred 1-dB compression point (P1dB) are -12.72 dBm and -20.9 dBm, respectively. The LNA core area occupies 0.353 mm2 and consumes 11.16 mW from a 1.8 V supply.

A novel low-complexity BPSK IR-UWB pulse generator in 0.13um CMOS technology

A new low-complexity energy-efficient impulse radio ultra-wideband (IR-UWB) pulse generator is investigated in the paper. It is designed and simulated in low-cost 0.13 μm UMC CMOS technology. The spectrum adjustable architecture consists of a tunable glitch generator, a BPSK modulator, two voltage controlled ring oscillators, an output buffer and a shaping filter. The simulation results showed spectrum that covers the higher UWB band and fully complies with the corresponding FCC spectral mask. The pulse duration is around 0.6 ns, and the peak-to-peak amplitude is 380 mV on 50 Ω output load. It has low power consumption of 0.44 mW corresponding to energy consumption of 2.2 pJ per pulse for 200 MHz pulse repetition frequency (PRF).

Inverter-based low-noise amplifier topologies for ultra-wideband applications

In this paper two ultra-wideband (UWB) low noise amplifier (LNA) configurations in UMC 0.18μm CMOS technology are presented. Both amplifiers are based on a shunt-feedback inverter-configuration with inductive peaking. In first LNA topology inductor is placed at the input node of the inverter cell. In the frequency range from 3.1 GHz - 10.6 GHz, this amplifier achieves power gain (S21) of 12.23 dB, noise figure of 5.62 dB and input/output return loss of -8 dB/-11 dB, while consuming 9.61 mA from 1.8 V supply. In second LNA peaking inductor is applied at the gate of NMOS transistor in inverter stage. With this technique the -3 dB roll-off frequency is increased from 9 GHz, obtained with previous technique, to 11.11 GHz, without additional power consumption. Achieved power gain from 3.1 GHz - 10.6 GHz is 12.64 dB, noise figure is 4.04 dB and input/output return loss is -7 dB/-10 dB. This amplifier consumes 9.48 mA from the 1.8 V supply.