Mirko Poljak

Assessment of Electron Mobility in Ultrathin-Body InGaAs-on-Insulator MOSFETs Using Physics-Based Modeling

We have investigated the electron mobility in ultrathin-body InGaAs-on-insulator devices using physics-based modeling that self-consistently accounts for quantum confinement and covers band-structure effects in ultrathin III-V layers. Scattering by nonpolar and polar acoustic and optical phonons, surface roughness, and thickness fluctuations, Coulomb and alloy disorder have been included in the calculations. The modeling, calibrated and verified on experimental data from the literature, has revealed a strong influence of thickness fluctuations caused by the light effective mass of Γ valley electrons. Our results indicate that InGaAs-on-insulator MOSFETs are more influenced by interface properties compared with silicon-on-insulator devices and outperform them only above certain body thickness that depends on interface quality.

SOI vs. bulk FinFET: Body doping and corner effects influence on device characteristics

SOI and bulk FinFET were analyzed by a three-dimensional numerical device simulator and their electrical characteristics were compared for different body doping and bias conditions. Subthreshold and on-state performance have been examined and higher drain current in case of SOI FinFET has been explained by investigating enhanced conduction in silicon-oxide interface corners.

Influence of Edge Defects, Vacancies, and Potential Fluctuations on Transport Properties of Extremely Scaled Graphene Nanoribbons

Atomistic quantum transport simulations of a large ensemble of devices are employed to investigate the impact of different sources of disorder on the transport properties of extremely scaled (length of 10 nm and width of 1-4 nm) graphene nanoribbons. We report the dependence of the transport gap, on- and off-state conductances, and on-off ratio on edge-defect density, vacancy density, and potential fluctuation amplitude. For the smallest devices and realistic lattice defect densities, the transport gap increases by up to ~300%, and the on-off ratio reaches almost ~106 . We also report a rather high variation of the transport gap and on-off ratio. In contrast, we find that the potential fluctuations have a negligible impact on the transport gap and cause a relatively modest increase of the on-off ratio.

Technological constrains of bulk FinFET structure in comparison with SOI FinFET

In order to obtain bulk FinFET characteristics that closely match SOI FinFET characteristics, meaning DIBL below 70 mV/V @ ID = 10-6 A and subthreshold swing below 100 mV/dec @ VDS = 1.2 V, source/drain junction depths must be aligned to the bottom of the gate and the fin width of the bulk FinFET must be 20 nm at most assuming the gate length of 50 nm. Bulk FinFET characteristics can be improved by reducing S/D junction depth with respect to the bottom of the gate (e.g. Deltaxj = -10 nm), which can be easily accomplished in fabrication.

Influence of substrate type and quality on carrier mobility in graphene nanoribbons

We report the results of a thorough numerical study on carrier mobility in graphene nanoribbons (GNRs) with the widths from ∼250 nm down to ∼1 nm, with a focus on the influence of substrate type (SiO2, Al2O3, HfO2, and h-BN) and substrate quality (different interface impurity densities) on GNR mobility. We identify the interplay between the contributions of Coulomb and surface optical phonon scattering as the crucial factor that determines the optimum substrate in terms of carrier mobility. In the case of high impurity density (∼1013 cm−2), we find that HfO2 is the optimum substrate irrespective of GNR width. In contrast, for low impurity density (1010 cm−2), h-BN offers the greatest enhancement, except for nanoribbons wider than ∼200 nm for which the mobility is highest on HfO2.

Immunity of electronic and transport properties of phosphorene nanoribbons to edge defects

We present an extensive study of the electronic properties and carrier transport in phosphorene nanoribbons (PNRs) with edge defects by using rigorous atomistic quantum transport simulations. This study reports on the size- and defect-dependent scaling laws governing the transport gap, and the mean free path and carrier mobility in the PNRs of interest for future nanoelectronics applications. Our results indicate that PNRs with armchair edges (aPNRs) are more immune to defects than zig-zag PNRs (zPNRs), while both PNR types exhibit superior immunity to defects relative to graphene nanoribbons (GNRs). An investigation of the mean free path demonstrated that even in the case of a low defect density the transport in PNRs is diffusive, and the carrier mobility remains a meaningful transport parameter even in ultra-small PNRs. We found that the electron–hole mobility asymmetry (present in large-area phosphorene) is retained only in zPNRs for W > 4 nm, while in other cases the asymmetry is smoothed out by edge defect scattering. Furthermore, we showed that aPNRs outperform both zPNRs and GNRs in terms of carrier mobility, and that PNRs generally offer a superior mobility-bandgap trade-off, relative to GNRs and monolayer MoS2. This work identifies PNRs as a promising material for the extremely scaled transistor channels in future post-silicon electronic technology, and presents a persuasive argument for experimental work on nanostructured phosphorene.

Quantum Transport Analysis of Conductance Variability in Graphene Nanoribbons With Edge Defects

We study the influence of edge defects and the downscaling of graphene nanoribbon (GNR) width (W) on the ON- and OFF-state conductance (G_ON and G_OFF) and the ON-OFF conductance ratio (G_ON/G_OFF). The averaged properties and the variability are explored by simulating ensembles of defected GNRs with various percentages of edge defects using atomistic quantum transport simulations. We find that even 10% edge defects decrease G_ON by at least 40%, even in the widest simulated GNRs, and that G_ON scales as ~W² for W > 3.2 nm and ~W⁹ for W <; 1.8 nm. The relative variability of G_ON (3σ compared with average) increases from ~30% to ~1000% when the width is scaled from 4.8 to 1.1 nm. Furthermore, while its variability can reach orders of magnitude, we find that there exists the optimum nanoribbon width range between 1.8 and 3.3 nm in terms of G_ON/G_OFF in GNRs with edge defects.

Features of electron mobility in ultrathin-body InGaAs-on-insulator MOSFETs down to body thickness of 2 nm

Behavior of electron mobility in UTB InGaAs-OI MOSFETs is studied by physics-based modeling. We have shown that UTB InGaAs-OI devices outperform Silicon-OI MOSFETs only for TS > 6.2 nm, due to high SR scattering. Therefore, improvement of interface quality remains crucial to utilize high electron mobility in extremely scaled InGaAs-OI devices.

Optimum body thickness of (111)-oriented ultra-thin body double-gate MOSFETs with respect to quantum-calculated phonon-limited mobility

Ultra-thin body (UTB) double-gate MOSFETs are foreseen as a solution to scaling issues for sub-20 nm CMOS due to excellent immunity to short-channel effects (SCEs). Transport mechanisms in UTB devices have been extensively investigated over the past years [1–3]. Nevertheless, theoretical considerations have been limited only to (100)-oriented UTB single- (SG) or double-gate (DG) devices while the experimental results are available mostly for (100)- and (110)-oriented SG SOI [2,3]. Therefore, an investigation of mobility-behavior in (111)-oriented UTB DG MOSFETs is neccessary, especially due to promising results of UTB FinFETs fabricated on (110) wafers with (111) active sidewalls [4].

Bulk-Si FinFET technology for ultra-high aspect-ratio devices

FinFETs with 1 µm tall fins have been processed on (110) bulk silicon wafers using crystallographic etching of silicon by TMAH to form fins with nearly vertical sidewalls of an (111) surface orientation. The concept of tall, narrow fins offers more efficient use of silicon area and better performance of multi-fin devices in high-frequency analog applications. N-channel FinFETs with 1.9-nm-wide fins and a height of the active part of the fin up to 650 nm have been fabricated and demonstrate the scaling potentials of the proposed technology. This extreme reduction of the fin width degrades electron mobility as compared to devices with 15-nm-wide fins, which have been used here to investigate the current conduction capability of FinFETs with (111) sidewalls.