Tomislav Suligoj

Assessment of Electron Mobility in Ultrathin-Body InGaAs-on-Insulator MOSFETs Using Physics-Based Modeling

We have investigated the electron mobility in ultrathin-body InGaAs-on-insulator devices using physics-based modeling that self-consistently accounts for quantum confinement and covers band-structure effects in ultrathin III-V layers. Scattering by nonpolar and polar acoustic and optical phonons, surface roughness, and thickness fluctuations, Coulomb and alloy disorder have been included in the calculations. The modeling, calibrated and verified on experimental data from the literature, has revealed a strong influence of thickness fluctuations caused by the light effective mass of Γ valley electrons. Our results indicate that InGaAs-on-insulator MOSFETs are more influenced by interface properties compared with silicon-on-insulator devices and outperform them only above certain body thickness that depends on interface quality.

Horizontal Current Bipolar Transistor With a Single Polysilicon Region for Improved High-Frequency Performance of BiCMOS ICs

A new horizontal current bipolar transistor (HCBT) with a single polysilicon region and a CMOS gate polysilicon near the n⁺ emitter region is integrated with CMOS technology with the addition of two or three masks (three or four masking steps) and a small number of additional fabrication steps. The single-poly HCBT with an optimized collector exhibits f_T and f_max of 51 and 61 GHz, respectively, and an f_TBV_CEO product of 173 GHz · V, which are the best reported HCBT characteristics to date and among the highest performance Si BJTs. An HCBT with only two additional masks to CMOS has f_T and f_max of 43 and 53 GHz, respectively, and an f_TSV_CEO product of 120 GHz · V. The developed innovative fabrication techniques enable a very low-cost BiCMOS platform for wireless communication circuits.

Fabrication of horizontal current bipolar transistor (HCBT)

The fabrication and characterization of very compact horizontal current bipolar transistor (HCBT) is presented. The active transistor region is processed in the sidewalls of the n-hill, which makes this structure attractive for the integration with pillar-like CMOS with minimum process additions. HCBT technology is simple with 5 lithography masks. The active n-hills are isolated by newly developed chemical-mechanical planarization (CMP) and etch back of oxide. The substrate is used for HCBT fabrication utilizing crystal planes as the active sidewalls. This enables the use of crystallographic dependent etchants for the minimization of the sidewall roughness and dry etching defects, as well as increases the controllability and repeatability of intrinsic transistor doping process. The active transistor regions are processed by angled ion implantation in self-aligned manner. The processed structures result in a cutoff frequency-breakdown voltage (f/sub T/BV/sub CEO/) product of 69.5 GHzV and current gain-Early voltage (/spl beta/V/sub A/) of 4800 V. The high-frequency characteristics are limited by the wide extrinsic base due to the coarse lithography resolution used for fabrication. It is shown by simulations that the improvement of (f/sub T/) and maximum oscillation frequency (f/sub max/) up to 24 and 50 GHz, respectively, can be achieved with finer lithography employed.

Collector region design and optimization in Horizontal Current Bipolar Transistor (HCBT)

Three different types of the n-collector region of Horizontal Current Bipolar Transistor (HCBT) are analyzed and compared. The optimum n-collector profile suppresses the charge sharing effect between the intrinsic and extrinsic base regions, resulting in the uniform base width and electric field in the intrinsic transistor. This implies a maximum BVCEO and an optimum fTBVCEO product among compared structures. The HCBT with a selectively implanted collector (SIC) is introduced and examined. It reduces RC and increases fT comparing to the other n-collector designs. The analyses give the guidelines for the optimum HCBT design for targeted applications.

Double-Emitter Reduced-Surface-Field Horizontal Current Bipolar Transistor With 36 V Breakdown Integrated in BiCMOS at Zero Cost

A novel double-emitter horizontal current bipolar transistor (HCBT) with reduced-surface-field (RESURF) region is presented. The structure is integrated with standard 0.18-μm CMOS, together with high-speed HCBT with BVCEO = 3.6 V and double-emitter HCBT with BVCEO = 12 V. The second RESURF drift region is formed using a standard CMOS p-well implant for the formation of local substrate below the extrinsic collector. Collector-emitter breakdown is completely avoided by the E-field shielding. Breakdown occurs between the collector and the substrate and equals 36 V. The transistor is fabricated in HCBT BiCMOS process flow without the additional process steps and the use of additional lithography masks.

SOI vs. bulk FinFET: Body doping and corner effects influence on device characteristics

SOI and bulk FinFET were analyzed by a three-dimensional numerical device simulator and their electrical characteristics were compared for different body doping and bias conditions. Subthreshold and on-state performance have been examined and higher drain current in case of SOI FinFET has been explained by investigating enhanced conduction in silicon-oxide interface corners.

Influence of Edge Defects, Vacancies, and Potential Fluctuations on Transport Properties of Extremely Scaled Graphene Nanoribbons

Atomistic quantum transport simulations of a large ensemble of devices are employed to investigate the impact of different sources of disorder on the transport properties of extremely scaled (length of 10 nm and width of 1-4 nm) graphene nanoribbons. We report the dependence of the transport gap, on- and off-state conductances, and on-off ratio on edge-defect density, vacancy density, and potential fluctuation amplitude. For the smallest devices and realistic lattice defect densities, the transport gap increases by up to ~300%, and the on-off ratio reaches almost ~106 . We also report a rather high variation of the transport gap and on-off ratio. In contrast, we find that the potential fluctuations have a negligible impact on the transport gap and cause a relatively modest increase of the on-off ratio.

Technological constrains of bulk FinFET structure in comparison with SOI FinFET

In order to obtain bulk FinFET characteristics that closely match SOI FinFET characteristics, meaning DIBL below 70 mV/V @ ID = 10-6 A and subthreshold swing below 100 mV/dec @ VDS = 1.2 V, source/drain junction depths must be aligned to the bottom of the gate and the fin width of the bulk FinFET must be 20 nm at most assuming the gate length of 50 nm. Bulk FinFET characteristics can be improved by reducing S/D junction depth with respect to the bottom of the gate (e.g. Deltaxj = -10 nm), which can be easily accomplished in fabrication.

Influence of substrate type and quality on carrier mobility in graphene nanoribbons

We report the results of a thorough numerical study on carrier mobility in graphene nanoribbons (GNRs) with the widths from ∼250 nm down to ∼1 nm, with a focus on the influence of substrate type (SiO2, Al2O3, HfO2, and h-BN) and substrate quality (different interface impurity densities) on GNR mobility. We identify the interplay between the contributions of Coulomb and surface optical phonon scattering as the crucial factor that determines the optimum substrate in terms of carrier mobility. In the case of high impurity density (∼1013 cm−2), we find that HfO2 is the optimum substrate irrespective of GNR width. In contrast, for low impurity density (1010 cm−2), h-BN offers the greatest enhancement, except for nanoribbons wider than ∼200 nm for which the mobility is highest on HfO2.

Horizontal current bipolar transistor (HCBT) process variations for future RF BiCMOS applications

Two different process designs of horizontal current bipolar transistor (HCBT) technology suitable for future RF BiCMOS circuits are presented. The active transistor region is built in the defect-free sidewall of 900-nm-wide n-hills on a [110] wafer. The collector n-hill region is partially etched at the extrinsic base-collector periphery, whereas the extrinsic base is self-protected, resulting in reduced collector-base capacitance (C/sub BC/) and minimized volume of the extrinsic regions. The effect of doping levels at different regions on the transistor performance is examined in the two process designs. The fabricated HCBTs exhibit cutoff frequencies (f/sub T/) from 19.2 to 25.6 GHz, maximum frequencies of oscillations (f/sub max/) from 32.2 to 39.6 GHz, and collector-emitter breakdown voltages (BV/sub CEO/) between 4 and 5.2 V, which are the highest f/sub T/ and the highest f/sub T//spl middot/BV/sub CEO/ product compared to existing silicon-on-insulator (SOI) lateral bipolar transistors (LBTs). The compact nature of the HCBT structure and low-cost technology make it suitable for integration with advanced pillar-like CMOS and SOI CMOS devices.