Graham A. Jullien

QCADesigner: a rapid design and Simulation tool for quantum-dot cellular automata

This paper describes a project to create a novel design and simulation tool for quantum-dot cellular automata (QCA), namely QCADesigner. QCA logic and circuit designers require a rapid and accurate simulation and design layout tool to determine the functionality of QCA circuits. QCADesigner gives the designer the ability to quickly layout a QCA design by providing an extensive set of CAD tools. As well, several simulation engines facilitate rapid and accurate simulation. This tool has already been used to design full-adders, barrel shifters, random-access memories, etc. These verified layouts provide motivation to continue efforts toward a final implementation of QCA circuits.

A method of majority logic reduction for quantum cellular automata

The basic Boolean primitive in quantum cellular automata (QCA) is the majority gate. In this paper, a method for reducing the number of majority gates required for computing three-variable Boolean functions is developed to facilitate the conversion of sum-of-products expression into QCA majority logic. Thirteen standard functions are introduced to represent all three-variable Boolean functions and the simplified majority expressions corresponding to these standard functions are presented. We describe a novel method for using these standard functions to convert the sum-of-products expression to majority logic. By applying this method, the hardware requirements for a QCA design can be reduced. As an example, a 1-bit QCA adder is constructed with only three majority gates and two inverters. The adder is designed and simulated using QCADesigner, a design and simulation tool for QCA. We will show that the proposed method is very efficient and fast in deriving the simplified majority expressions in QCA design.

Quantum-dot cellular automata adders

In this paper, a novel quantum-dot cellular automata (QCA) adder design is presented that reduces the number of QCA cells compared to previously reported designs. The proposed one-bit QCA adder structure is based on a new algorithm that requires only three majority gates and two inverters for the QCA addition. By connecting n one-bit QCA adders, we can obtain an n-bit carry look-ahead adder with the reduced hardware while retaining the simple clocking scheme and parallel structure of the original carry look-ahead approach. The proposed adder is designed and simulated using the QCA Designer tool for the four-bit adder case. The proposed design requires only about 70% of the hardware compared to previous designs with the same speed and clocking performance.

A Wireless-Implantable Microsystem for Continuous Blood Glucose Monitoring

A remotely powered implantable microsystem for continuous blood glucose monitoring is presented. The microsystem consists of a microfabricated glucose biosensor flip-chip bonded to a transponder chip. The transponder chip is inductively powered by an external reader with a 13.56-MHz carrier. It then measures the output signal of the glucose biosensor and transmits the measured data back to the external reader using load-shift keying (LSK). The microsystem has a volume of 32 mm3. The procedures for the microfabrication of the glucose sensor and the assembly of the microsystem are described along with the description of the circuit blocks of the transponder chip. The transponder chip has been fabricated with the TSMC 0.18-mum CMOS process and has a total area of 1.3 x 1.3 mm2. The chip can measure the sensor output current ranging from 1 nA to 1 muA with less than 0.3% nonlinearity error, provided that the amplitude of the received RF signal is higher than 2.6 V; the circuit consumes a total current of about 110 muA.

Design Tools for an Emerging SoC Technology: Quantum-Dot Cellular Automata

The future of system-on-chip (SoC) technologies, based on the scaling of current FET-based integrated circuitry, is being predicted to reach fabrication limits by the year 2015. Economic limits may be reached before that time. Continued scaling of electronic devices to molecular scales will undoubtedly require a paradigm shift from the FET-based switch to an alternative mechanism of information representation and processing. This paradigm shift will also have to encompass the tools and design culture that have made the current SoC technology possible-the ability to design monolithic integrated circuits with many hundreds of millions of transistors. In this paper, we examine the initial development of a tool to automate the design of one of the promising emerging nanoelectronic technologies, quantum-dot cellular automata, which has been proposed as a computing paradigm based on single electron effects within quantum dots and molecules.

Current-Mirror-Based Potentiostats for Three-Electrode Amperometric Electrochemical Sensors

We present a new circuit topology for potentiostats that interface with three-electrode amperometric electrochemical sensors. In this new topology, a current-copying circuit, e.g., a current mirror, is placed in the sensor current path to generate a mirrored image of the sensor current. The mirrored image is then measured and processed instead of the sensor current itself. The new potentiostat topology consumes very low power, occupies a very small die area, and has potentially very low noise. These characteristics make the new topology very suitable for portable or bioimplantable applications. In order to demonstrate the feasibility of the new topology, we present the results of a potentiostat circuit implemented in a 0.18-mum CMOS process. The circuit converts the sensor current to a frequency-modulated pulse waveform, for which the time difference between two consecutive pulses is inversely proportional to the sensor current. The potentiostat measures the sensor current from 1 nA to 1 muA with better than 0.1% of accuracy. It consumes only 70 muW of power from a 1.8-V supply voltage and occupies an area of 0.02 mm2.

Fast adders using enhanced multiple-output domino logic

Using an enhanced multiple output domino logic (EMODL) implementation of a carry lookahead adder (CLA), sums of several consecutive bits can be built in one nFET tree with a single carry-in. Based on this result, a new sparse carry chain architecture is proposed for the CLA adder. We demonstrate the design approach using a 32-b adder, and show that only four carries are sufficient for generating all sums, with a consequent reduction in the number of stage delays. Using a 1.2-/spl mu/m CMOS technology, we verify our simulation procedures by fabrication and measurement of a 2.7 ns critical path.

Performance comparison of quantum-dot cellular automata adders

QCA adders are fundamental building blocks of complex QCA computational units. In our analysis, we show that QCA ripple-carry adder and bit-serial adder designs actually outperform carry-look-ahead and carry-select adder designs. The QCA ripple-carry and bit-serial adders require fewer clocking zones, which have been found to be the main contributing factor toward overall circuit latency.

Circuit design based on majority gates for applications with quantum-dot cellular automata

Majority gate-based logic is not normally explored with standard CMOS technologies, primarily because of the hardware inefficiencies in creating majority gates. As a result, not much effort has been made towards the optimization of circuits based on majority gates. We are exploring one particular emerging technology, quantum-dot cellular automata (QCA), in which the majority gate is the fundamental logic primitive. We report a simple and intuitive method for reduction of three-variable Boolean functions into a simplified majority representation. The method is based on Karnaugh maps (K-maps), used for the simplification of Boolean functions.

High Level Exploration of Quantum-Dot Cellular Automata (QCA)

In this work, we present a high level evaluation of an emerging nanotechnology to determine a set of technology requirements. The technology under question is Quantum-Dot Cellular Automata (QCA). As a vehicle, we present two different QCA circuits and evaluate the technology requirements based on the specifications of these circuits. These circuits are a simple 4-bit arithmetic logic unit (ALU) and a 4/spl times/4 memory which are building blocks to more complex systems such as a computer central processing unit (CPU).