Mitsuo Higuchi

A 150ns 288k CMOS EPROM with redundancy

needed, with a power supply of +21V to program cell data. Programming pulse width has now been reduced to 2ms, affording a total pulsewidth for 32K words of one minute. By using fine pattern lithography, optimized scaling and a self-determined source structure of memory cells (Figure 1 ) the cell area has been reduced to 54

An 80ns address-date multiplex 1mb CMOS EPROM

. The channel length of the peripheral circuits is 2p for N-channel transistors and a longer channel length is used for P-channel transistors. Operation is fully static and no external c ock is needed. Inputs and outputs are TTL compatibleduring both read and program modes. Two line control with CE and OE is maintained in an 8-bit device. In an 8-b&device, programming is obtainedLy applying TTL low pulse to CE input when V is at 21V and OE is TTL high. Program verific&on can be per?!rmed by applying a low level signal to ?%?and OE inputs even when Vpp is 21V. This paper wiJl report on a 288K (2.5610 CMOS EPROM with

Semiconductor memory device with decoder for chip selection/write in

This report will cover an EPROM organized as 64K×16b. Precharging techniques achieved an access time of 80ns Light-shielded cells control switching of redundant word lines.