Kiyoshi Miyasaka

A 1Mb DRAM with 3-dimensional stacked capacitor cells

pads in the center of the chip, permit assembly within a 300mil 18 pin plastic DIP and 300mil26 pin plastic Small Outline J-lead package (SOJ). The cell structure is shown in Figure 1. First layer polycide forms the wordline. The second layer poly-Si, which forms the storage node, is extended over its own wordline and the next wordline. The third layer poly-Si, which forms the cell plate, is spread over the second layer poly-Si. The cell capacitor is formed between the second and third layer poly-Si. Bitline is formed by AI. Since the capacitor is formed over the wordlines, the address The chip layout, with peripheral circuitry and some of the

A sub 100ns 256Kb DRAM

A 256K DRAM with nibble-mode and<tex>\overline{CAS}</tex>before<tex>\overline{RAS}</tex>refresh will be described. Triple-poly-si processing is used only with 2.5μ layout rules for a die size of 34.1mm².

A 150ns 288k CMOS EPROM with redundancy

needed, with a power supply of +21V to program cell data. Programming pulse width has now been reduced to 2ms, affording a total pulsewidth for 32K words of one minute. By using fine pattern lithography, optimized scaling and a self-determined source structure of memory cells (Figure 1 ) the cell area has been reduced to 54

A 35ns 64K static column DRAM

. The channel length of the peripheral circuits is 2p for N-channel transistors and a longer channel length is used for P-channel transistors. Operation is fully static and no external c ock is needed. Inputs and outputs are TTL compatibleduring both read and program modes. Two line control with CE and OE is maintained in an 8-bit device. In an 8-b&device, programming is obtainedLy applying TTL low pulse to CE input when V is at 21V and OE is TTL high. Program verific&on can be per?!rmed by applying a low level signal to ?%?and OE inputs even when Vpp is 21V. This paper wiJl report on a 288K (2.5610 CMOS EPROM with

Semiconductor memory device with decoder for chip selection/write in

A 64K by l b DRAM with multiplexed address inputs, packaged in a standard 300-mil wide 16 pin DIP, but with only one address strobe clock (RAS), will be reported. After one row address is selected with the RAS clock, as in normal multiplexed devices, column address selection (one of the 2561, boundarylrow) can be performed in a manner similar to static memory: data from the output changes in accordance with the change of column address without an address strobe clock. Access time from the columnzdress, and cycle time are typically 3511s. The deaffords CS (Chip select) instead of column address strobe (CAS), enabling or disabling the output at high speed. Typical chip select access time is less than 12ns. In write operation the falling edge of write enable (WE) latches the column address and Data In, and the write operation period extends automatically to the time when the device indicates the completion of writing; write time out. Following read or write operation starts immediately according to the state of WE. Figure 1 illustrates the concept of static column operation. The storage cells, sense amplifiers, and row decoders are almost the same as those of current 64K DRAMS. The sense amplifiers are fully dynamic with active pull up circuits. Word lines are pushed above Vcc to utilize the full charge of cells.