Mitsuo Usami

An ultra small individual recognition security chip

The manufacturing and distribution of goods requires good quality and inventory control. The RFID (radiofrequency identification) enabled microchips small size and low cost make it suitable for attachment to paper media and small products, aiding counterfeit prevention and product tracking in market environments.

Powder LSI: an ultra small RF identification chip for individual recognition applications

A powder-like 0.09 mm/sup 2/ 2.45 GHz RF identification chip for wireless recognition applications is described. This chip is fabricated in a 0.18 /spl mu/m CMOS process, and its thickness is 60 /spl mu/m. A two-surface connection technique is adopted to facilitate antenna attachment. The distance between the chip and a reader is 300 mm for a reader power of 300 mW.

A 0.05×0.05mm2 RFID Chip with Easily Scaled-Down ID-Memory

An ultra-small RFID chip uses an electron beam for writing 1T memory cells. A 90nm SOI CMOS process and double-surface electrode chip structures enable the design of 0.05times0.05mm2 and 5mum-thick RFID chips with small, low-cost and highly-reliable 128b ID-memory. The chip is verified at a carrier frequency of 2.45GHz with measured communication distance of 300mm.

An ultra-small RFID chip: /spl mu/-chip

An ultra-small (0.3 /spl times/ 0.3 /spl times/ 0.06 mm) radiofrequency identification chip, called the /spl mu/-chip, has been developed for use in a wide range of individual recognition applications. The chip is designed to be thin enough to be applied to the paper and paper-like media widely used in retailing to create certificates that have monetary value, as well as to tokens. It was designed and fabricated using 0.18-/spl mu/m standard CMOS technology.

Bonding of IC bare chips for microsystems using Ar atom bombardment

This paper describes integrated circuit (IC) bare chip bonding to micromechanical devices and discusses factors affecting bond and IC qualities. Test element group (TEG) with protective diode and TEG with transistors, small-scale circuits and junctions were used here as the IC chips. Some of the TEG dies were thinned into films. In the bonding process, an Ar atom beam is used to sputter clean the surface to be bonded. After contaminants on the surfaces to be bonded are removed by the Ar atomic beam irradiation, the IC chip, a die or a film is bonded to a silicon substrate. The IC dies and the films can be bonded at low temperature and under low pressure. The strengths of the joints are good enough for use in microsystems. There is no difference in current-voltage properties of the IC films before and after the irradiation. The shapes of the ring osillator waves of the bonded IC films are not distorted by the thermal tests. This suggests that the thermal tests do not cause electrical damage to the IC chips. Although the joints of IC film/Si substrate have a few fine voids at the interface, the thermal conductivities of the joints are compared to those of IC films before bonding. The results given show the feasibility of mounting bare IC chips onto substrates of microsystems.

Water-based high-volume stress-free ultra-thin powder-chip method

We propose fabrication and subsequent packaging processes for ultra-small and ultra-thin (75×75×7.5 µm) radio frequency identification (RFID)-chips (called “RFID powder chips”). To fabricate a chip with no chipping and micro-cracks and to increase the chip yield per wafer, self-etch-stop thinning and 5-µm narrow dicing were performed using anisotropic dry etching in a SOI-wafer based process. Consequently, a damage-less 7.5-µm-thick RFID powder chip with an Au-coated double-surface electrode structure was obtained. The structure of the surface electrodes has the advantage that, when mounting the powder chip on an external antenna film for the packaging process, the chips are just placed in a relatively large electric-contact area on the antenna without the need for highly accurate positioning, orientation, and side surface controls. A technological issue for the packaging process is how to handle the powder chip. Because the chips not only form aggregated structures from electrostatic and van der Waals forces in a dry environment, but also are mechanically brittle, the conventional pick-up technique is unfeasible. Accordingly, we have developed a new water-based, stress-free chip handling technique. In this technique, the chips are kept dispersed by liquid stirring, and only a single chip is captured and manipulated using a micropipette. The water-based chip capturing process strongly depends on dispersion and mobility controls of the chips. Yield rates for various liquid solutions and stirring speeds were investigated. Addition of 0.5% non-ionic surfactant to the powder chip stock solutions effectively prevented chips from sticking together. Also, high capture rates above 90% were obtained with stirring speeds ranging from 1000 to 1200 rpm. The positioning accuracy of the chip placing process was also investigated. Using robotic actuators with repeatable positioning accuracies of above +/− 50 µm in chip manipulation, a 100% success rate was obtained in the case of the square placing-area of 300 µm. During pick-up and place operation, no chip breakage was observed.

Powder RFID chip technology

Ultra-small radio frequency identification (RFID) chip with its antenna technology is described. The key techniques used in this ultra-small chip to reduce chip size and cost are embedded antenna, double-surface electrode and silicon on insulator (SOI).

Ultra-Small RLID Chip Technology

Ultra-small radio frequency identification (RFID) chip with its antenna technology is described. The key techniques used in this ultra-small chip to reduce chip size and cost are embedded antenna, double-surface electrode and silicon on insulator (SOI).

The World’s Smallest RFID Chip Technology

Ultra-small radio frequency identification (RFID) chip and antenna technology are described. The key technologies used in this ultra-small chip to reduce chip size and cost are embedded antenna, electron beam (EB) memory, double-surface electrode and silicon on insulator (SOI).

An SOI-Based 7.5/spl mu/m-Thick 0.15x0.15mm2 RFID Chip

A 0.15times0.15mm2 RFID chip containing a 128b ROM is fabricated in a 0.18mum 4M SOI CMOS technology. It achieves 480mm read range with a 2.45GHz carrier for a reader output power of 300mW. The chip is thinned precisely by using an SOI buried oxide layer structure as an etch stop. An RFID antenna is connected to the chip by using a double-surface electrode