Mitsuru Sometani

Improved Channel Mobility in 4H-SiC MOSFETs by Boron Passivation

We propose another process for fabricating 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with high channel mobility. The B atoms were introduced into a SiO2/4H-SiC interface by thermal annealing with a BN planar diffusion source. The interface state density near the conduction band edge of 4H-SiC was effectively reduced by the B diffusion and the fabricated 4H-SiC MOSFETs showed a peak field-effect mobility of 102 cm2/Vs. The obtained high channel mobility cannot be explained by counter doping because B atoms act as acceptors in 4H-SiC. We suggest that the interfacial structural change of SiO2 may be responsible for the reduced trap density and enhanced channel mobility.

Temperature-dependent analysis of conduction mechanism of leakage current in thermally grown oxide on 4H-SiC

The conduction mechanism of the leakage current of a thermally grown oxide on 4H silicon carbide (4H-SiC) was investigated. The dominant carriers of the leakage current were found to be electrons by the carrier-separation current-voltage method. The current-voltage and capacitance-voltage characteristics, which were measured over a wide temperature range, revealed that the leakage current in SiO2/4H-SiC on the Si-face can be explained as the sum of the Fowler-Nordheim (FN) tunneling and Poole-Frenkel (PF) emission leakage currents. A rigorous FN analysis provided the true barrier height for the SiO2/4H-SiC interface. On the basis of Arrhenius plots of the PF current separated from the total leakage current, the existence of carbon-related defects and/or oxygen vacancy defects was suggested in thermally grown SiO2 films on the Si-face of 4H-SiC.

Threshold-voltage instability in 4H-SiC MOSFETs with nitrided gate oxide revealed by non-relaxation method

The threshold-voltage (V th) shift of 4H-SiC MOSFETs with Ar or N2O post-oxidation annealing (POA) was measured by conventional sweep and non-relaxation methods. Although the V th shift values of both samples were almost identical when measured by the sweep method, those for the Ar POA samples were larger than those for the N2O POA samples when measured by the non-relaxation method. Thus, we can say that investigating the exact V th shifts using only the conventional sweep method is difficult. The temperature-dependent analysis of the V th shifts measured by both methods revealed that the N2O POA decreases charge trapping in the near-interface region of the SiO2.

Low V f and highly reliable 16 kV ultrahigh voltage SiC flip-type n-channel implantation and epitaxial IGBT

Flip-type n-channel implantation and epitaxial (IE)-IGBT on 4H-SiC carbon face with an epitaxial p++ collector layer was investigated. In this study, we employed the IEMOSFET as a MOSFET structure with original wet gate oxidation method, to realize high channel mobility. We were able to achieve an ultrahigh blocking voltage of more than 16 kV, extremely low forward voltage drop of 5 V at 100 A/cm2 and small threshold voltage shift (<; 0.1 V). These characteristics are useful for Smart Grid and HVDC systems, the use of which would realize a low carbon emission society.

Characterization of traps at nitrided SiO2/SiC interfaces near the conduction band edge by using Hall effect measurements

The effects of nitridation on the density of traps at SiO2/SiC interfaces near the conduction band edge were qualitatively examined using a simple, newly developed characterization method that utilizes Hall effect measurements and split capacitance–voltage measurements. The results showed a significant reduction in the density of interface traps near the conduction band edge as a result of nitridation, but the interface traps were not completely eliminated by nitridation.

Device Performance and Switching Characteristics of 16 kV Ultrahigh-Voltage SiC Flip-Type n-Channel IE-IGBTs

Ultrahigh-voltage SiC flip-type n-channel implantation and epitaxial (IE)-IGBTs were developed, and the static and dynamic performance was investigated. A large device (8 mm × 8mm) with a blocking voltage greater than 16 kV was achieved, and an on-state current of 20 A was obtained at the low on-state voltage (Von) of 4.8 V. RonAdiff was 23 mΩ·cm2 at Von = 4.8 V. In order to evaluate the switching characteristics of the IE-IGBT, ultrahigh-voltage power modules were assembled. A chopper circuit configuration was used to evaluate the switching characteristics of the IE-IGBT. Smooth turn-off waveforms were successfully obtained at VCE = 6.5 kV and ICE = 60 A in the temperature range from room temperature to 250°C.

Exact Characterization of Threshold Voltage Instability in 4H-SiC MOSFETs by Non-Relaxation Method

In this work, we investigated the methods that measure the threshold voltage (Vth) instability without relaxation of the gate stress during the Vth measurement. We propose a non-relaxation method that demonstrates exact Vth shifts compared with conventional methods that are not as accurate. In the non-relaxation method, the constant gate-source voltage (Vgs) is continuously applied as a gate stress while the drain voltage (Vds) shift required to maintain a constant drain current (Id) is measured. Then, the Vds shift is converted to a Vth shift. The Vth shift values measured by the non-relaxation method are larger than those measured by the other methods, which means that the non-relaxation method can very accurately measure the Vth shift.

Self-aligned formation of the trench bottom shielding region in 4H-SiC trench gate MOSFET

To suppress the electric field in the gate oxide in a trench gate MOSFET (UMOSFET) with small cell pitch, we developed a technique to form the p+ region using self-aligned ion implantation under the gate trench. To prevent Al+ injection into the trench sidewalls, conditions of thin oxide layer deposition and Al+ implantation were optimized by process simulation. The resulting SiC trench MOS capacitors exhibited long-term reliability, with no degradation in lifetime by the p+ shielding region, and a specific on-resistance of 9.4 mΩ cm2 with a blocking voltage of 3800 V was achieved in the UMOSFET.

Characterization of traps in SiC/SiO2 interfaces close to the conduction band by deep-level transient spectroscopy

The effects of the oxidation atmosphere and crystal faces on the traps in SiC/SiO2 interfaces close to the conduction band were investigated by deep-level transient spectroscopy. It was found that a high density of traps was observed around the energy of 0.16 eV from the edge of the conduction band in interfaces oxidized in a N2O atmosphere on the Si-face (O1 traps) and C-face (C1 traps). From the comparison of their energies, it was concluded that the O1 traps and C1 traps had the same origin. We also found that C1 traps were eliminated only on the C-face by wet oxidation. The simulation using the obtained energy and density of C1 traps in the interface oxidized in a N2O atmosphere on the C-face showed that the trapping of electrons in C1 was predominant just after the onset of the formation of an inversion layer, where the total electron density generated by the gate voltage was less than 7 × 1011 cm−2.

Characterization of near-interface traps at 4H-SiC metal–oxide–semiconductor interfaces using modified distributed circuit model

We characterized the near-interface traps (NITs) in SiO2/4H-SiC structures according to the distributed circuit model, which was originally proposed for Al2O3/InGaAs interface structures. We assumed that the NITs had an exponentially decaying distribution from the SiO2/4H-SiC interface into the oxide, rather than the uniform trap distribution of the conventional model. Using this model with the exponential NIT distribution as a basis, we successfully explained the frequency-dependent characteristics of both the capacitance and conductance in the strong-accumulation condition with reasonable physical parameters. We also observed that nitridation annealing over a long period of time significantly reduced the NIT density distribution.