Dai Okamoto

Improved Inversion Channel Mobility in 4H-SiC MOSFETs on Si Face Utilizing Phosphorus-Doped Gate Oxide

We propose a new technique for fabricating 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with high inversion channel mobility. P atoms were incorporated into the SiO₂/4H-SiC (0001) interface by postoxidation annealing using phosphoryl chloride (POCl₃). The interface state density near the conduction band edge of 4H-SiC was reduced significantly, and the peak field-effect mobility of lateral 4H-SiC MOSFETs on (0001) Si face was improved to 89 cm²/V · s by POCl₃ annealing at 1000°C.

Removal of near-interface traps at SiO2/4H–SiC (0001) interfaces by phosphorus incorporation

Effective removal of near-interface traps (NITs) in SiO2/4H–SiC (0001) structures through phosphorus incorporation is demonstrated in this paper. Low-temperature capacitance-voltage and thermal dielectric relaxation current measurements were employed to investigate NITs in oxides prepared by dry oxidation, NO annealing, and POCl3 annealing. Both the measurements revealed that the density of electrons trapped in NITs in POCl3-annealed oxide is smaller than that in dry and NO-annealed oxides. The drastic elimination of NITs lowers the interface state density and increases the channel mobility in 4H–SiC metal-oxide-semiconductor field-effect transistors.

Improved Channel Mobility in 4H-SiC MOSFETs by Boron Passivation

We propose another process for fabricating 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with high channel mobility. The B atoms were introduced into a SiO2/4H-SiC interface by thermal annealing with a BN planar diffusion source. The interface state density near the conduction band edge of 4H-SiC was effectively reduced by the B diffusion and the fabricated 4H-SiC MOSFETs showed a peak field-effect mobility of 102 cm2/Vs. The obtained high channel mobility cannot be explained by counter doping because B atoms act as acceptors in 4H-SiC. We suggest that the interfacial structural change of SiO2 may be responsible for the reduced trap density and enhanced channel mobility.

Development of Ultrahigh-Voltage SiC Devices

Ultrahigh-voltage silicon carbide (SiC) devices [p-i-n diodes and insulated-gate bipolar transistors (IGBTs)] and switching test have been investigated. As a result, we have succeeded in developing a 13-kV p-i-n diode, 15-kV p-channel IGBT, and 16-kV flip-type n-channel implantation and epitaxial IGBT with a low differential specific on-resistance (Rdiff,on). It was revealed that a power module fabricated using a nanotech resin, Si3N4 ceramic substrate, and W base plate was suitable for ultrahigh voltage and high temperature. A switching test was carried out using a clamped inductive load circuit, which indicated that the energy loss of a circuit with ultrahigh-voltage SiC devices is lower than that of Si devices.

Temperature-dependent analysis of conduction mechanism of leakage current in thermally grown oxide on 4H-SiC

The conduction mechanism of the leakage current of a thermally grown oxide on 4H silicon carbide (4H-SiC) was investigated. The dominant carriers of the leakage current were found to be electrons by the carrier-separation current-voltage method. The current-voltage and capacitance-voltage characteristics, which were measured over a wide temperature range, revealed that the leakage current in SiO2/4H-SiC on the Si-face can be explained as the sum of the Fowler-Nordheim (FN) tunneling and Poole-Frenkel (PF) emission leakage currents. A rigorous FN analysis provided the true barrier height for the SiO2/4H-SiC interface. On the basis of Arrhenius plots of the PF current separated from the total leakage current, the existence of carbon-related defects and/or oxygen vacancy defects was suggested in thermally grown SiO2 films on the Si-face of 4H-SiC.

Instability of 4H-SiC MOSFET Characteristics due to Interface Traps with Long Time Constants

Instability of metal-oxide-semiconductor field-effect transistor (MOSFET) characteristics was evaluated by DC and pulse current-voltage (I-V) measurements. MOSFETs with nirided gate oxides were fabricated on C-face 4H-SiC. Their interfaces have near interface traps (NITs) with long time constants, depending on the cooling down process after nitridation. Such devices exhibited a large hysteresis in DC I-V and a large transient current in pulse I-V measurements. These phenomena can be explained by the charge state of NITs due to capture/emission of electrons in the channel.

Analysis of Anomalous Charge-Pumping Characteristics on 4H-SiC MOSFETs

Anomalous charge-pumping characteristics of 4H-silicon carbide (SiC) MOSFETs were analyzed. Charge-pumping measurements of n- and p-channel 4H-SiC MOSFETs with and without NO annealing were performed. Measurements using various pulse fall times revealed that the geometric component exists in the n-channel 4H-SiC MOSFETs and is particularly large in the unannealed n-channel 4H-SiC MOSFETs with low channel mobility. In addition, influence of interface states on the charge-pumping curves is significant in the unannealed 4H-SiC MOSFETs. The charge-pumping curves are distorted by these two nonideal effects, making the analysis of the charge-pumping curves difficult. A sufficiently long pulse fall time, which is on the order of 1-10 mus for the n-channel 4H-SiC MOSFETs with a 10-mum gate length, is required to minimize the effect of the geometric component.

Threshold-voltage instability in 4H-SiC MOSFETs with nitrided gate oxide revealed by non-relaxation method

The threshold-voltage (V th) shift of 4H-SiC MOSFETs with Ar or N2O post-oxidation annealing (POA) was measured by conventional sweep and non-relaxation methods. Although the V th shift values of both samples were almost identical when measured by the sweep method, those for the Ar POA samples were larger than those for the N2O POA samples when measured by the non-relaxation method. Thus, we can say that investigating the exact V th shifts using only the conventional sweep method is difficult. The temperature-dependent analysis of the V th shifts measured by both methods revealed that the N2O POA decreases charge trapping in the near-interface region of the SiO2.

Development of High-Voltage 4H-SiC PiN Diodes on 4° and 8° Off-Axis Substrates

13-kV 4H-SiC PiN diodes were fabricated on 4° and 8° off-axis substrates and their electrical properties were examined. Small test PiN diodes with various JTE concentrations were fabricated and the dependence of JTE concentration was examined. The highest breakdown voltages were 14.6 and 14.1 kV at a JTE1 concentration of 1.9 × 1017 cm−3 for both the 4° and 8° off-axis substrates. Based on the results, 4 mm × 4 mm SiC PiN diodes were successfully fabricated and exhibited avalanche breakdown voltages of 14.0 and 13.5 kV for the 4° and 8° off-axis substrates, respectively. Forward voltage degradation was larger for the 8° off-axis substrates.

Systematic Investigation of Interface Properties in 4H-SiC MOS Structures Prepared by Over-Oxidation of Ion-Implanted Substrates

A change in the interface state density in 4H-SiC metal–oxide–semiconductor (MOS) structures by incorporation of various elements was systematically investigated. B, N, F, Al, P, and Cl ions were implanted prior to the oxidation and introduced at the SiO2/SiC interface by subsequent thermal oxidation. Interface state density near the conduction band edge for Al-, B-, F-, and Cl-implanted MOS capacitors increased with implantation dose. On the other hand, a strong reduction of the interface state density was observed for N- and P-implanted samples when the implantation dose was larger than 5.0 × 1012 cm−2. It was found that the interface state density can be reduced by P as well as N.