Mitsuyasu Kido

Development of distributed relaying processor with digital filtering of fast sampled data

In order to cope with advanced relaying techniques, a multimicroprocessor-based digital relay was developed. The main features are distributed processing among five processors, 32-b floating-point operations, digital filtering of fast sampled data, and a personal computer based testing tool. Performance tests of this digital relay showed the following characteristics: (1) the error of any relaying element (distance, overcurrent and undervoltage) was less than 1%; (2) operating time was less than 20 ms when the processing interval was 1.67 ms; and (3) a single relaying processor had a computational capacity of six-phase (ground, short*4 steps*3 phases) distance relays based on differential equations, accompanying elements, and a self-diagnosis function in every processing interval. >

A triple redundant controller which adopts the time-sharing fault recovery method and its application to a power converter controller

A novel fault recovery method, in which memory copy from a normal system to a fault detected system is executed in time-sharing fashion, has been implemented in a triple redundant controller. This method reduces data copy bandwidth required for recovery of the fault detected system, and allows non-stop fault recovery with only a little hardware overhead, even when the controller contains multiple processors and operates at a very short operating period. The developed controller contains triplicated processing units, each of which consists of seven 60 MIPS processor boards connected by a 30 MHz 4 byte bus. One processor board contains a bus arbiter, and each of the remaining six processor boards contains three sets of 100 Mbps two-way optical links, which can be utilized for inter-system memory copy as well as for connecting to 10 units. This controller has been applied to a power converter controller, and a 104 microsecond operating period was achieved.

Development of custom LSIs for protective relays and their evolution to new static relays

A relay LSI and a filter LSI are developed for static distance relays. The relay LSI is based on the phase-comparison scheme and applicable to a reactance relay, a mho relay, an offset mho relay, and an ohm relay. Key technologies used to meet the relay requirements are CMOS switched-capacitor technologies. Circuit compositions and characteristic test results are described. A prototype relay unit demonstrated superiority to a conventional unit in terms of its compactness. High reliability (because of the small number of parts), high accuracy, and very low power dissipation. >

Time synchronization for real-time control systems without PTP-enabled switches

IEEE 1588 is a promising way of time synchronization in control systems that include IT. Intermediate devices such as network switches are needed when the control systems are built on a multi-hop network for wide area operations. However, the introduction of switches causes conflicts between the reply packets from the devices in a switch, and thus, the delays on the backward and forward paths would be different and the synchronization accuracy is degraded as a result. On the other hand, it is difficult to build low cost control systems when using dedicated switches for the precision time protocol (i.e., boundary clock or transparent clock). Therefore, the authors propose a method that estimates the conflicts between synchronization packets based on the observable information by using the synchronization master device and applies the estimation to the synchronization method. We used communication evaluation board to create a prototype for the proposed method and then evaluated it. The results showed that the level of accuracy was ±1μs accuracy under five slaves and that there was a 2-msec cyclic time synchronization.

NS-3 based IEEE 1588 synchronization simulator for multi-hop network

Network time synchronization using IEEE 1588 has tended to be applied to a wide network(i.e. a multi-hop network) with the aid of IEEE 1588 version 2 enhancement. However, designing a system to fulfill the desired synchronization accuracy is difficult because there are many factors that have an impact on multi-hop networks. Therefore, we developed a time synchronization simulator based on the network simulator 3 (NS-3) by developing a clock conversion model, IEEE 1588 simulation model, and application model with activation coordinated with synchronized time.