Mohamed Abouelatta

Speeding-up Phase-Locked Loops based on Adaptive Loop Bandwidth

paper describes three techniques for controlling the loop filter of the PLL for high operating speed. The proposed fast- locking PLL reduces the pull-in time and enhances the switching speed, while maintaining better noise bandwidth. Extended loop bandwidth enhancement is achieved by the adaptive control on the loop filter resistances. This work differs from previously published results in that it presents a comprehensive study for modeling, circuit simulation and practical circuit implementation of a 2nd order PLL with loop filter control for speeding-up the PLL. The overall improvement in performance of the proposed PLL is evaluated and compared with the conventional PLL. An industrial CMOS IC is used to implement the PLL.

Impact of TSV location in HVIC on CMOS operation: A mixed-mode TCAD simulation study

Abstract In this paper, a stacked 3D-technology is proposed to integrate the high voltage (HV) cLDMOS with the low voltage (LV) CMOS using TSV. The impact of the (0.0/42.0 V) HV signal of the future automotive applications on the performance of the LV CMOS inverter, implemented on the standard 0.35 μm BiCMOS technology, is investigated. This impact is performed utilizing a mixed mode simulation by using an equivalent SPICE models for the CMOS devices and finite element method (FEM) for the bulk regions. The CMOS output current is taken as an indicator for the substrate perturbations due to the switching of the applied signals. It is demonstrated that the influence of the HV on the performance of the CMOS signal is dependent on the location of the TSV. This effect can be minimized by adding a P + guard-ring between the pMOS device and the TSV using the same mask of the nMOS P-WELL active area.

Design and simulation of proposed low cost solar cell structures based on heavily doped silicon wafers

This paper aims to present the design and simulation of two proposed low cost solar cell structures; namely, pn and npn. Both structures are based on commercially available low cost heavily doped silicon wafers. Their operation relies on the idea of vertical generation and lateral collection of the light generated carriers. A detailed qualitative analysis of both structures is given and verified using advanced TCAD tools. The comparison is analyzed firstly regarding the illuminated IV characteristics. The open circuit voltage (Voc), short circuit current density (Jsc), fill factor (F.F) and conversion efficiency (η) are calculated. Additionally, the optical performance is calculated and compared for both structures. The quantum efficiency, the spectral response and the absorption curve are compared. The presented results show that npn structure gives better electrical and optical performance than the pn one.

Modeling and simulation of a hybrid 3D silicon detector system using SILVACO and Simulink/MATLAB framework

In this paper, a system of a hybrid pixel detector has been developed. The purpose is to create a flexible and reliable model that simulates the entire system, starting from a 3D detector to a data acquisition system and processing analysis. The model flexibility is achieved by minimizing interdependencies among its entities, so they can be added or removed as needed. The implementation of the system is accomplished using SILVACO and Simulink/MATLAB. The 3D detector is simulated using SILVACO to investigate its electrical performance. It is designed such that to have a good charge collection efficiency, position resolution and reduced charge sharing effects. Simulink is used to implement the readout circuit. The front-end readout circuit includes the Charge Sensitive Amplifier (CSA) and Active Shaper. The most suitable approach and parameters for a real system are selected according to the simulation results. Additionally, practical design constraints are also included in the model.

On design of M2M smart energy control and management architecture using smart metering technology

Nowadays, energy consumption becomes a focus domain for governorates and organizations around the world, due to the increasing rate of carbon dioxide gas footprint resulting from traditional resources of energy in addition to the significant limitation of energy resources. Accordingly, the world is obliged to save energy and manage consumption, which allow safe environment, through eco-sustainable systems that best utilize and shape the energy consumption profile. In this paper, a technique based on smart metering standard is developed to optimize the consumption of energy in homes and factories, and thus enable cost-effective operation of electricity grid at distribution segments. The proposed architecture allows both the user and electricity company to control loads at distribution areas based on energy consumption classes and thus enables two main types of control, namely tariff/billing based control and load profile control in addition to the switch-off for loads based on overload cases. The Machine-to-Machine (M2M) concept is adopted whereas the sensory devices talks to the controlling server and negotiate the consumption in light of pre-set preferences without human intervention. The technology allows a measured energy data to be sent, stored, analyzed, and managed for usage. A pilot is prepared and tested as a proof of concept for the impact on energy savings as a result of adopting the proposed system.

High quality tunable Brillouin optoelectronic oscillator

An optical scheme to improve the quality of an RF signal is proposed. The 6 dB linewidth is reduced to sub hertz and the low frequency noise below 1 KHz is reduced about 10 dB. The scheme utilizes a Brillouin-semiconductor optical amplifier (SOA) ring laser fitted with an RF intensity modulator and an APD detector. The experimental results show cavity modes with FSR of 30.57 KHz due to Brillouin fiber length of 6.6 km and 6 dB bandwidth of 780 mHz typical of Brillouin lasers. The gain of the SOA balances out most of the losses in the ring mainly that due to the RF modulator. The modulated optical signal beats at the APD. The optical loop acts as a cavity filter to the RF signal. A jitter in the cavity resonances due to temperature variations is completely eliminated from the output beat signal. There is a 10 dB increase in the phase noise at the FSR frequency and its harmonics. The setup is tested with signals generated by different sources and to frequencies up to 10 GHz, the limit of the APD. Sources with RF linewidth less than the optical FSR produces one output mode with sub-hertz line width. For larger line width signals more than one RF frequency is produced, separated by the FSR, each showing the Brillouin linewidth.

Implementing a Standard DVB-T System using MATLAB Simulink

This paper describes the Simulink implementation of all functional blocks of a standard Digital Video Broadcasting Terrestrial (DVB-T) transmitter and receiver and presents the simulation model for DVB-T system according to ETSI EN 300 744 V1.6.1. The implemented model contains all channel coding and modulation building blocks with the parameters: 8K OFDM-mode, code rate (1/2, 2/3, and 3/4), and Modulation (64-QAM, 16-QAM). Realizing such system level implementation is required to study the effect of the channel on the transmission properties of the system and it helps getting the required quality of service by adjusting the system parameters. In addition, such model is the first step in software defined radio implementation. The bit error rate as a function of the signal to noise ratio C/N is evaluated to be used in the link budget calculations. General Terms DSP System, DVB-T, Computer Applications

Automatic Measurements of the Performance Parameters of Practical Phase-Locked Loops

ABSTRACT An important issue in PLL design and manufacture is to simulate, measure, and verify its performance and key parameters for achieving goals of good time and frequency domain responses, as well as good noise and jitter performance. In this paper, we will introduce our new method that is capable of simulating and measuring automatically the PLL key parameters, such as the hold-in range and the pull-in range. Performance parameters for the PLL, such as loop gain, damping factor, natural frequency and settling time, can be simulated and measured concurrently. This method will help to shorten the time of measurements. This work presents an automatic testing method for the PLL using circuit simulator and practical circuit implementation. An industrial CMOS PLL is used to implement the PLL. Good agreement between the simulation and experimental is results is found. General Terms Electronic design, Communications, Simulation, Hardware Keywords