Mohamed Ali

FM-UWB transmitter for wireless body area networks: Implementation and simulation

This paper describes an implementation of low power frequency modulated ultra-wideband (FM-UWB) transmitter in standard 130nm CMOS technology. The transmitter is designed to operate in the range of 3.328-4.608 GHz. A relaxation oscillator is used to generate the subcarrier signal which is calibrated by a phase-locked loop (PLL). The RF carrier is generated using a voltage-controlled oscillator (VCO). A proposed calibration scheme based on a PLL is utilized to calibrate both the upper and the lower frequencies of the operation band. The proposed FM-UWB transmitter consumes 835μW from a 1.2V supply at 500kbps achieving an energy efficiency of 1.67nJ/bit.

A Survey on FM-UWB Transceivers

his paper surveys the research on frequency modulated ultra- wideband (FM-UWB) transceivers. FM-UWB system uses low modulation index digital FSK followed by high modulation index analog FM to generate a constant envelope UWB signal with a flat power spectral density and steep spectral roll-off. FM-UWB can be seen as an analog implementation of a spread spectrum system with spreading gain equal to the modulation index. FM-UWB system is suitable for low data rate and short-range applications. The advantages of FM-UWB system such as low power consumption, very low radiated power (−41.3 dBm/MHz), good coexistence with other existing wireless technologies, and robustness to interference and multipath making it suitable for Wireless Body Area Network (WBAN) in medical applications.

Ultra-low power 3.5–4.5GHz FM-UWB transmitter

This paper presents a novel ultra-low power FM-UWB transmitter implemented in 130nm CMOS process. The transmitter operates in the range of 3.5-4.5GHz with 4GHz RF carrier frequency. The transmitter can accept input data rates up to 250kbps. It consists of a relaxation oscillator to generate the subcarrier signal and a VCO for RF carrier generation. The center frequency of the VCO is periodically calibrated by an integer-N phase-locked loop (PLL). The PLL takes only 300ns to complete the calibration. The simulated VCO phase noise is - 79dBc/Hz at 1MHz offset. The proposed FM-UWB transmitter consumes (power amplifier is not included) about 50μW for a 1.2V supply.

A 14.5 µW generic Carrier Width demodulator for telemetry-based Medical Devices

This paper investigates a Carrier Width Modulation (CWM) demodulator designed mainly for batteryless Implantable Medical Devices. The proposed circuit architecture is a generic demodulator; designed to operate at 27.12 MHz while supporting a wide range of data rates. It allows low power consumption, small silicon area and high immunity against noise and amplitude disturbance. A simplified CWM demodulator architecture and a corresponding fully integrated implementation elaborated using the 130 nm IBM CMOS technology are reported. Post-layout simulation results confirm the effectiveness of the CWM demodulator for wireless power transfer and downlink communication. The proposed CWM demodulator can reach data rates up to 1/3 of the carrier frequency, i.e., 9.04 Mbit/s in this case. The circuit occupies an 1826 µm2 silicon area and dissipates 14.5 µW, in worst conditions, when operating from a 1.2 V power supply. For lower data rates, it consumes less power and allows higher power transfer during communication through an inductive link.

Stability of GaN150-based HEMT in high temperature up to 400°C

The first high-temperature characterization of GaN150 HEMT devices is presented from ambient temperature to 400°C. With a 2-gate length of 150nm, three configurations of GaN150 are investigated. They have gate widths of 40µm (T<inf>1</inf>), 100µm (T<inf>2</inf>) and 200µm (T<inf>3</inf>) respectively. The stability with temperature of the electrical characteristics of the AlGaN/GaN devices are measured with tungsten probes while the tested die is heated by a hot plate. The packaging is a standard tungsten based metallization, with Ni and Au plating, supporting a 92% alumina ceramic substrate. The drain saturation current decreases from 50mA, 150mA and 290mA at room temperature (RT) to 35mA, 110mA and 175mA at 400°C for T<inf>1</inf>, T<inf>2</inf> and T<inf>3</inf> respectively. The peak transconductance value of T<inf>1</inf> is dropped from 22mS at ambient temperature to 8mS at 250°C. The pinch-off voltage is stable at VGS = −5V during the whole temperature change.

PLL based BFSK subcarrier generator for FM-UWB transmitter

This paper presents the implementation, the layout and the post-layout simulation of two main blocks of the FM-UWB transmitter; the voltage-controlled oscillator (VCO) and the subcarrier generator. A low power and linear ring VCO is proposed to generate the RF signal. A low power PLL based BFSK subcarrier generator is introduced. It includes a linear relaxation oscillator to produce the subcarrier signal. The circuits are implemented in 130nm CMOS technology. The data rate is 500kbps. Post-layout simulations show that the PLL consumes only 306μW while the VCO consumes 300μW from a 1.2V supply. The area of the PLL is 0.0124mm2.

Quad-Level Carrier Width Modulation demodulator for micro-implants

Due to their growing potential, Implantable Medical Devices (IMDs) are getting more complex and thus require more sophisticated wireless powering and communication systems. This paper introduces a new modulation technique based on pulse width modulation for data transmission across inductive links. The technique is called Quad-Level Carrier Width Modulation (QCWM). It allows high data-rate transmission and ultra low power consumption, while maintaining a simple implementation. A very simple fully integrated QCWM demodulator circuit is implemented using 130 nm IBM CMOS technology. Post-layout simulation results validate the feasibility of the proposed technique and show ultra-low power consumption of 35.5 μW drawn from a supply voltage of 1.2V when transmitting data at a rate of 10.85 Mbps.

Amplitude demodulation based on synchronized sampling by a PLL circuit

In this paper, we present a new radio frequency receiver dedicated for avionic signals which can be used for distance measuring and air control traffic system. The designed system, based on the direct radio frequency sampling approach, uses a smart sampling to digitize and demodulate the received signal at the same time. The presented design is composed of a Phase-Locked Loop and a Delta-Sigma modulator and integrated in a 130 nm CMOS technology. Matlab simulations demonstrate the sensitivity of the system to the jitter and its effect on reliability. Using circuit simulation under Cadence environment, we have proved that our design achieved the expected demodulation performance with a low clock jitter.