Mohamed El-Hadedy

High Performance Implementation of a Public Key Block Cipher - MQQ, for FPGA Platforms

This is the first implementation in FPGA of the recently published class of public key algorithms - MQQ, that are based on quasigroup string transformations. Our implementation achieves decryption throughput of 399 Mbps on an Xilinx Virtex-5 FPGA that is running on 249.4 MHz. The encryption throughput of our implementation achieves 44.27 Gbps on an Xilinx Virtex-5 chip that is running on 276.7 MHz. Compared to RSA implementation on the same FPGA platform this implementation of MQQ is 10,000 times faster in decryption, and is more than 17,000 times faster in encryption. The main goal of this work was to build a hardware that can perform operations with the public and the private key that have as high as possible speed. Our main comparison is with RSA with a similar cryptographic strength, because we want to emphasize that RSA being essentially sequential algorithm can not benefit from the parallel capabilities that modern FPGAs offer, while MQQ can.

π -Cipher: Authenticated Encryption for Big Data

In today’s world of big data and rapidly increasing telecommunications, using secure cryptographic primitives that are parallelizable and incremental is becoming ever more important design goal. π-Cipher is parallel, incremental, nonce based authenticated encryption cipher with associated data. It is designed with the special purpose of providing confidentiality and integrity for big data in transit or at rest. It has, as an option, a secret part of the nonce which provides noncemisuse resistance. The design involves operations of several solid cryptographic concepts such as the Encrypt-then-MAC principle, the XOR MAC scheme and the two-pass sponge construction. It contains parameters that can provide the functionality of tweakable block ciphers for authenticated encryption of data at rest. The security of the cipher relies on the core permutation function based on ARX (Addition, Rotation and XOR) operations. π-Cipher offers several security levels ranging from 96 to 256 bits.

Resource-efficient implementation of Blue Midnight Wish-256 hash function on Xilinx FPGA platform

This paper presents the design and analysis of an area efficient Blue Midnight Wish compression function with digest size of 256 bits (BMW-256) on FPGA platforms. The proposed architecture achieves significant improvements in system throughput with reduced area. We demonstrate the performance of the proposed BMW hash function core using VIRTEX 5 FPGA implementation. The new BMW hash function design allows for 16X speed up in performance while consuming significantly lower area than previously reported (i.e. just 445 slices).

Area efficient processing element architecture for compact hash functions systems on VIRTEX5 FPGA platform

This paper presents the design and analysis of an area efficient processing element structure for use in cryptographic systems especially for implementing hash functions. The proposed architecture achieves significant efficiency improvements based on a reduction in area. We demonstrate a compact processing element on FPGA. As a proof of concept, we employed that compact processing element in the implementation of the Blue Midnight Wish (BMW) hash function which is one of the fastest candidates in the 2nd round SHA-3 hash function competition when implemented in software. With our new processing element, on Xilinx Virtex-5 we implemented BMW-256 in just 51 slices achieving a throughput of 68.71 Mbps and BMW-512 in just 105 slices achieving a throughput of 112.18 Mbps. Our design of the new processing element (PE) require the use of block RAM memory for storing the internal structure of the hash functions as well as for the PE instruction logic.

Implementing the Blue Midnight Wish Hash Function on Xilinx Virtex-5 FPGA Platform

This paper presents the design and analysis of an area efficient implementation of the SHA-3 candidate Blue Midnight Wish (BMW-256) hash function with digest size of 256 bits on an FPGA platform. Our architecture is based on a 32 bit data-path. The core functionality with finalization implementation without padding stage of BMW on Xilinx Virtex-5 FPGA requires 84 slices and two blocks of memory: one memory block to store the intermediate values and hash constants and the other memory block to store the instruction controls. The proposed implementation achieves a throughput of 56 Mpbs.

Performance and area efficient transpose memory architecture for high throughput adaptive signal processing systems

This paper presents the design and analysis of a power and area efficient transpose memory structure for use in adaptive signal processing systems. The proposed architecture achieves significant improvements in system throughput over competing designs. We demonstrate the throughput performance of the proposed memory on FPGA as well as ASIC implementations. The memory was employed in a watermarking architecture previously proposed. The new memory design allows for 2X speed up in performance for the watermarking algorithm and up to 10X speedup for 2D DCT and IDCT algorithms compared to previously published work, while consuming significantly lower power and area.

Low latency transpose memory for high throughput signal processing

This paper presents the design and analysis of a power and area efficient, low latency transpose memory structure for use in adaptive signal processing systems. The proposed architecture achieves significant improvements in system throughput over competing designs. We demonstrate the throughput performance of the proposed memory on FPGA as well as ASIC implementations. The memory was employed in a watermarking architecture previously proposed. The new memory design allows for 2X speed up in performance for the watermarking algorithm and up to 10X speedup for 2D DCT and IDCT algorithms compared to previously published work, while consuming significantly lower power and area.

Low area FPGA and ASIC implementations of the hash function “Blue Midnight Wish-256”

Hash functions are widely used in information security and cryptography. They are used in countless applications such as message authentication codes (MAC), Digital Signatures (DS) and mobile trusted modules (MTM). Serious attacks have been reported against cryptographic hash algorithms, including SHA-1. Because the SHA-1 and SHA-2 families share a similar design, the National Institute of Standards and Technology (NIST) in 2007 decided to start a world-wide development process for choosing the next secure hash standard SHA-3. A pivotal part of the process is an open competition for bringing forward new and secure cryptographic hash functions. The Blue Midnight Wish hash function is one of the second round candidates for the SHA-3 competition. In this paper, we describe low area FPGA and ASIC implementations for the Blue Midnight Wish compression function with digest size of 256 bits (BMW-256). Using Xilinx FPGA platform Virtex 5 “XC5VLX30”, we implemented BMW-256 using 1986 slices (including the internal memory), and using only 122 slices for an implementation that uses external memory. By using 0.8 µm CMOS standard cell library the ASIC implementation of BMW-256 takes approximately 13.5 Kgates (including the internal memory), and only 4 Kgates for an implementation that uses external memory.

An Efficient Authorship Protection Scheme for Shared Multimedia Content

Many electronic content providers today like Flickr and Google, offer space to users to publish their electronic media(e.g. photos and videos) in their cloud infrastructures so that they can be publicly accessed. Features like including other information, such as keywords or owner information into the digital material is already offered by existing providers. Despite the useful features made available to users by such infrastructures, the authorship of the published content is not protected against various attacks such as compression. In this paper we propose a robust scheme that uses digital invisible watermarking and hashing to protect the authorship of the digital content and provide resistance against malicious manipulation of multimedia content. The scheme is enhanced by an algorithm called MMBEC, that is an extension of an established scheme MBEC towards higher resistance.