Mohamed H. Zaki

Review: Formal verification of analog and mixed signal designs: A survey

Analog and mixed signal (AMS) designs are an important part of embedded systems that link digital designs to the analog world. Due to challenges associated with its verification process, AMS designs require a considerable portion of the total design cycle time. In contrast to digital designs, the verification of AMS systems is a challenging task that requires lots of expertise and deep understanding of their behavior. Researchers started lately studying the applicability of formal methods for the verification of AMS systems as a way to tackle the limitations of conventional verification methods like simulation. This paper surveys research activities in the formal verification of AMS designs as well as compares the different proposed approaches.

A symbolic methodology for the verification of analog and mixed signal designs

The paper proposed a new symbolic verification methodology for proving the properties of analog and mixed signal (AMS) designs. Starting with an AMS description and a set of properties and using symbolic computation, a normal mathematical representation was extracted for the system in terms of recurrence equations. These normalized equations are used along with an induction verification strategy defined inside the computer algebra system Mathematica to prove the correctness of the properties. The methodology was applied on a third order DeltaSigma modulator

A tool converting finite state machine to VHDL

Finite state machines (FSM) are a basic component in hardware design; they represent the transformation between inputs and outputs for sequential designs. FSMs can be represented graphically, which would help the designer to visualize and design in a more efficient way; on the other hand the designer requires a fast direct way to convert the visualized design to hardware description language (HDL) code directly in order to simulate and implement it for synthesis and analysis. In this paper, we present a tool which, starting from a graphical FSM representation, produces a behavioral HDL code which can be directly analyzed and synthesized.

Formal Verification of Analog and Mixed Signal Designs: Survey and Comparison

Analog and mixed signal (AMS) circuits are important integrated circuits that are usually needed at the interface between the electronic system and the real world. In contrast to digital designs, verification of AMS systems is a challenging task that requires lots of expertise and deep understanding of their behavior. Researchers started lately studying the applicability of formal methods for the verification of AMS systems as a way to tackle the limitations of conventional verification methods like simulation. This paper surveys research activities in the formal verification of AMS designs as well as compares the different proposed approaches.

A practical approach for monitoring analog circuits

Formal methods have been advocated for the verification of digital design where correctness is proved mathematically. In contrast to digital designs, the verification of analog and mixed signal systems is a challenging task that requires lots of expertise and deep understanding of their behavior. In this paper, we present a run-time verification methodology based on monitoring the behavior (solution flow) of analog circuits. Monitors are deterministic timed automata that can be synthesized from temporal properties. For illustration purposes, we applied our methodology on the verification of the oscillation property of a tunnel diode oscillator.

Towards improving simulation of analog circuits using model order reduction

Large analog circuit models are very expensive to evaluate and verify. New techniques are needed to shorten time-to-market and to reduce the cost of producing a correct analog integrated circuit. Model order reduction is an approach used to reduce the computational complexity of the mathematical model of a dynamical system, while capturing its main features. This technique can be used to reduce an analog circuit model while retaining its realistic behavior. In this paper, we present an approach to model order reduction of nonlinear analog circuits. We model the circuit using fuzzy differential equations and use qualitative simulation and K-means clustering to discretion efficiently its state space. Moreover, we use a conformance checking approach to refine model order reduction steps and guarantee simulation acceleration and accuracy. In order to illustrate the effectiveness of our method, we applied it to a transmission line with nonlinear diodes and a large nonlinear ring oscillator circuit. Experimental results show that our reduced models are more than one order of magnitude faster and accurate when compared to existing methods.

On the simulation performance of contemporary AMS hardware description languages

Mixed-Signal extensions to VHDL, Verilog, and SystemC languages have been developed in order to provide a unifying environment for the modeling and verification of Analog and Mixed Signal (AMS) designs at different levels of abstraction. In this paper, we model the behavior of a set of benchmark designs in VHDL-AMS, Verilog-AMS and SystemC-AMS and compare the simulation performance with HSPICE. The various experimental results observed for the benchmark circuits show the superiority of VHDL-AMS and Verilog-AMS against SystemC-AMS and HSPICE in terms of simulation runtimes at lower level of abstraction.

Syntax code analysis and generation for Verilog

In this paper, we present a syntax analyser tool for Verilog programs which can be used as a front end to debugging and program verification tools.

Towards flight control verification using automated theorem proving

To ensure that an aircraft is safe to fly, a complex, lengthy and costly process must be undertaken. Current aircraft control systems verification methodologies are based on conducting extensive simulations in an attempt to cover all worst-case scenarios. A Nichols plot is a technique that can be used to conclusively determine if a control system is stable. However, to guarantee stability within a certain margin of uncertainty requires an informal visual inspection of many plots. To leverage the safety verification problem, we present in this paper a method for performing a formal Nichols Plot analysis using the MetiTarski automated theorem prover. First the transfer function for the flight control system is extracted from a Matlab/Simulink design. Next, using the conditions for a stable dynamical system, an exclusion region of the Nichols Plot is defined. MetiTarski is then used to prove that the exclusion region is never entered. We present a case study of the proposed approach applied to the lateral autopilot of a Model 24 Learjet.

Checking properties of PLL designs using run-time verification

Due to challenges associated with its verification process, analog and mixed signal designs like PLLs require a considerable portion of the total design time. In this paper, we propose a run-time verification approach for PLL designs. The essence of this approach is to monitor properties of interest by timed automata integrated within an automatic stimulus generation framework. The objective is to guide simulation by an appropriate simulation trace in order to quickly detect errors by the property monitor.