Ghiath Al Sammane

Verification of analog and mixed signal designs using online monitoring

Analog and mixed signal (AMS) circuits play an important role in todays System on Chip design. They pose, however, many challenges in the verification of the overall system due to their complex behavior. Among many developed verification techniques, runtime verification has been shown to be effective by experimenting finite executions instead of going through the whole state space. In this paper, we present a methodology for the specification and verification of AMS designs using online monitoring at runtime based on the notion of System of Recurrence Equations (SREs). We implement the proposed methodology in a C language based tool, called C-SRE, and utilize it to verify several properties of a PLL design. We compare our proposed online monitoring techniques with the offline approach. Finally, we apply the proposed methodology to monitor the jitter noise associated with a voltage controlled oscillator.

Reachability analysis using multiway decision graphs in the HOL theorem prover

In this paper, all the necessary infrastructure is provided to define a state exploration approach within the HOL theorem prover. While related work has tackled the same problem by representing primitive Binary Decision Diagram (BDD) operations as inference rules added to the core of the theorem prover, the presented approach is based on the Multiway Decision Graphs (MDGs). MDG generalizes BDD to represent and manipulate a subset of first-order logic formulae. Considering MDG instead of BDD will raise the abstraction level of what can be verified using states exploration within a theorem prover. A canonic MDGs is defined in HOL as well-formed directed formulae. Then, the basic MDG operations is formalized following a deep embedding approach and the correctness proof for each operation is derived. Finally, the reachability analysis is implemented as a tactic that uses the MDG theory within HOL.

Automatic verification of reduction techniques in Higher Order Logic

In this paper we propose an automatic methodology to verify the soundness of model checking reduction techniques. The idea is to use the consistency of the specifications to verify if the reduced model is faithful to the original one. The user provides the reduction technique, the specification and the system under verification. Then, using Higher Order Logic he verifies automatically if the reduction technique is soundly applied. The method is completely defined in an MDG–HOL special integration platform that combines an automatic high level model checking tool Multiway Decision Graphs (MDGs) within the HOL theorem prover. We provide two case studies, the first one is the reduction using SAT–MDG of an Island Tunnel Controller and the second one is the MDG–HOL assume-guarantee reduction of the Look-Aside Interface. The obtained results of our approach offer a considerable gain in terms of the correctness of heuristics and reduction techniques as applied to commercial model checking, however a small penalty is paid in terms of CPU time and memory usage.