Mohamed M. Hafed

A 4-GHz effective sample rate integrated test core for analog and mixed-signal circuits

An area-efficient and robust integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstruction filter and a comparator. It is capable of both generating arbitrary band-limited waveforms (for excitation purposes) and coherently digitizing arbitrary periodic analog waveforms (for DSP-based test and measurement). Several prototypes were fabricated in a triple-metal 3.3-V 0.35-/spl mu/m CMOS process, and were demonstrated to perform various curve tracing, oscilloscope, and spectrum analysis tasks at a clock rate of 20 MHz (limited by our experimental setup). Designed for 8 bits of quantization, a spurious-free dynamic range (SFDR) of 65 dB at 500 KHz and 61 dB at Nyquist (20.001 MHz) was demonstrated using our prototypes. High-frequency narrow-band signals (extending into the gigahertz range) have been captured through subsampling and the use of a high-bandwidth front-end sampling network. Similarly, circuit phenomena that are broadband in nature were measured by using a delayed-clock subsampling mechanism in which the digitizer sample clock is consistently delayed over multiple runs of the periodic test signal. Delaying the clock is performed using a voltage-controlled delay line tuned by a self-biased delay-locked loop, which allowed for a timing resolution of about one gate delay (/spl sim/200 ps). The proposed test core occupies an area equivalent to only about 7000 standard-cell 2-input NAND gates.

A stand-alone integrated test core for time and frequency domain measurements

An area efficient and robust integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstruction filter and a comparator. It is capable of both generating arbitrary band-limited waveforms (for excitation purposes) and coherently digitizing arbitrary periodic analog waveforms (for DSP-based test and measurement). A prototype IC was fabricated in a 3.3 V 0.35 /spl mu/m CMOS process. It was demonstrated to perform various curve tracing, timing, and spectrum analysis tasks at a sampling frequency of 20 MHz (which was only limited by our experimental setup) while taking up an area equivalent to only about five thousand standard-cell 2-input NAND gates.

A stand-alone integrated excitation/extraction system for analog BIST applications

An integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstruction filter and a comparator. It is capable of both generating arbitrary band-limited waveforms (for excitation purposes) and coherently digitizing arbitrary periodic analog waveforms (for DSP-based test and measurement). A prototype IC was fabricated in a 0.35 /spl mu/m CMOS process and was demonstrated to perform various curve tracing, oscilloscope, and spectrum analysis tasks.

Strategies for on-chip sub-nanosecond signal capture and timing measurements

Two strategies for on-chip signal capture and characterization are described. The first is an extension of an integrated mixed-signal test core that has the ability to provide time and frequency domain measurements. This extension consists of a Delay Locked Loop (DLL) based timing module that through an undersampling algorithm provides high effective sampling rates for arbitrary, high bandwidth, periodic signals. The second is a time to digital converter (TDC) based on a Vernier Delay Line (VDL). This circuit can sample digital signals at very fine time intervals, and produce an on-chip jitter cumulative distribution function (CDF) from which a jitter histogram may be extracted. Both techniques were successfully demonstrated using a prototype IC in a 0.35 /spl mu/m CMOS process.

Massively Parallel Validation of High-Speed Serial Interfaces using Compact Instrument Modules

An extremely dense high-speed serial interface validation tester is presented. By relying on parallelism and on efficient measurement techniques, the proposed tester significantly reduces the time to validate the key parameters for serdes interfaces such as the bit error rate, receiver sensitivity, receiver jitter tolerance, and transmit jitter generation. Key timing specifications include periodic jitter injection with less than 5 psec edge-placement resolution and jitter measurement with 160 fsec sampling delay resolution

Test and evaluation of multiple embedded mixed-signal test cores

The simultaneous operation of multiple embedded analog test cores is investigated through experiments on a prototype integrated circuit containing eight such cores. Each core consists of a scan memory, some passive filters, and a fully synchronized integrated waveform digitizer for signal extraction. The circuit supports fully differential signal generation and digitization and employs common circuit techniques to enhance robustness to process variation. Simultaneous operation is demonstrated to achieve over 12-bits of amplitude resolution and more than 70 dB SFDR over a 20 MHz bandwidth. Matching issues are investigated, and instrument uniformity across about 250 cores is verified by measuring waveform generator offset errors, digitizer offset errors, and test core frequency response variability.

A robust deep submicron programmable DC voltage generator

An efficient technique for generating accurate on-chip DC reference voltages is presented. The technique is based on filtering a digital pulse-modulated sequence in order to extract its average (DC) value. Simplicity is achieved by using a passive on-chip filter and by using an all-digital implementation of the modulator. Moreover, in addition to using pulse-width modulation to encode the value of the output DC level, we propose the use of pulse-density modulation as a more viable technique. The latter has the advantage of using a significantly smaller filter, which translates into a smaller implementation area and a faster settling time. The technique was successfully demonstrated using a prototype IC in a 0.35 /spl mu/m CMOS process.

A 5-channel, variable resolution, 10-GHz sampling rate coherent tester/oscilloscope IC and associated test vehicles

An integrated circuit uses a 0.18 /spl mu/m CMOS process and contains five 10-GHz effective sampling rate analog-tester/oscilloscope cores. Each core consists of a memory, two samplers, and a voltage comparator. It can perform coherent DSP-based testing of mixed-signal macros and transient measurement for signal integrity evaluation. Each such core supports a variable resolution of up to 9-b. Test vehicles, such as a tuned amplifier, on-chip interconnect, and digital noise generators, are measured using the cores.

Sigma-delta techniques for integrated test and measurement

An area efficient and robust integrated test core for analog and mixed-signal circuits is described. The core consists of two signal generators that approximate the output of a sigma-delta modulator using finite repetitious bit patterns. When these structures are coupled with simple filtering techniques and using minimal analog components, the resulting system is capable of performing many measurement functions typical of spectrum analyzers, multimeters, and oscilloscopes.

An 8-channel, 12-bit, 20 MHz fully differential tester IC for analog and mixed-signal circuits

An 8-channel mixed-signal tester integrated circuit that is suitable for very low footprint test applications is described. It is capable of simultaneously stimulating eight analog or mixed-mode devices under test and coherently digitizing eight device responses at an amplitude resolution of 12-b and a bandwidth of 20-MHz. The circuit is fabricated in a 2.5 V, 0.25 /spl mu/m CMOS process, and achieves a SFDR of over 70 dB at 20 MHz with a maximum DNL of 0.15 LSB. It owes its compactness to a versatile, mostly digital architecture that is easily synthesizable. Software-based performance evaluation and calibration is also described.