Gordon W. Roberts

A BIST scheme for an SNR test of a sigma-delta ADC

Built-In-Self-Test (BIST) for VLSI systems is desirable in order to reduce the cost per chip of production-time testing by the manufacturer. In addition, it can provide the means to perform in-the-field diagnostics. This paper discusses a mixed analog-digital BIST (MADBIST) for a signal-to-noise-ratio test of an analog-to-digital converter. The MAD-BIST strategy for the SNR test of the A/D converter is introduced, accuracy issues are discussed, and experimental results are presented.<<ETX>>

A BIST scheme for a SNR, gain tracking, and frequency response test of a sigma-delta ADC

Built-in-self test (BIST) for VLSI systems is desirable in order to reduce the cost per chip of production-time testing by the manufacturer. In addition, it can provide the means to perform in-the-field diagnostics. This paper discusses a mixed analog-digital BIST (MADBIST) for a signal-to-noise-ratio test, gain tracking test, and frequency response test of a sigma-delta analog-to-digital converter. The MADBIST strategy for the SNR, GT, and FR tests of the ADC is introduced, accuracy issues are discussed, and experimental results are presented. >

The design of log-domain filters based on the operational simulation of LC ladders

A technique for the design of log-domain filters is introduced which is based on the operational simulation of LC ladders. The method is used to design a fifth-order Chebyshev and elliptic filter. HSPICE simulation results and experimental results are shown with emphasis on frequency behavior and linearity. The filters showed good correlation between the original filter specifications and the measured frequency response. They proved to be easily tunable and could be operated up to 1 MHz or one tenth of the f/sub T/ of the slowest transistor. Total harmonic distortion and intermodulation distortion was measured with results up to -47 and -55 dB, respectively.

On-chip analog signal generation for mixed-signal built-in self-test

A new method for generating analog signals with very low complexity and hardware requirements has recently been introduced. It consists of periodically reproducing short optimized bitstreams recorded from the output of a sigma-delta modulator. In this paper, various types of signals generated using the bitstream approach are discussed. Two different silicon implementations are presented, and their performance is analyzed through experimental results. Various ways in which the generators can be used are also demonstrated. Emphasis is placed on the simplicity of the design process and its compact implementation, which are crucial considerations when implementing a built-in self-test strategy.

A general class of current amplifier-based biquadratic filter circuits

A general class of current amplifier-based biquadratic filter circuits capable of realizing arbitrary filter functions including the low-pass, high-pass, and bandpass transfer functions is presented. These realizations are derived from a class of well-known low sensitivity single amplifier biquadratic (SAB) filter circuits using the principle of adjoint networks. The salient features of the proposed circuits are that they are synthesized using the same procedure as their op-amp-based SAB circuit counterparts, and they possess the same sensitivities to component variations as the original SAB circuits. However, it is demonstrated experimentally that unlike op-amp-based SAB realizations whose effective operating bandwidth is much less than the unity-gain bandwidth of the op-amp, these current-based filter circuits are effective over the entire bandwidth of the current amplifier. >

A jitter characterization system using a component-invariant Vernier delay line

Jitter characterization has become significantly more important for systems running at multigigahertz data rates. Time and frequency domain characterization of jitter is thus a crucial element for system specification testing. Time domain jitter measurement on a data signal with subgate timing resolution can be achieved using two delay chains feeding into the clock and datalines of a series of D-latches known as a Vernier delay line (VDL). An important drawback to the VDL structure is that its measurement accuracy depends on the matching of the various delay elements. Although careful layout techniques can help to minimize these mismatches, it cannot eliminate them completely. As well, due to the nature of the design, a relatively large silicon area is required for silicon implementation. In this paper, a novel technique is developed which reduces the silicon area requirements by two orders of magnitude, as well enables the measurement device to be synthesized from a register transfer level (RTL) description. A custom IC was designed and fabricated in a 0.18-/spl mu/m CMOS process as a first proof of concept. The design requires a silicon area of 0.12 mm/sup 2/ and measured results indicate a timing resolution of 19 ps. The synthesizable nature of the design is demonstrated using an field-programmable gate-array implementation. As test time is an important consideration for a production test, an extension to the component-invariant VDL technique is provided that reduces test time at the expense of more hardware. Finally, a method for obtaining the frequency domain characteristics of the jitter using the VDL will also be given.

A Brief Introduction to Time-to-Digital and Digital-to-Time Converters

This paper presents a short review of time-to-digital and digital-to-time converters (TDCs and DTCs, respectively) adopting a time-mode signal-processing perspective. The primary definitions, operating principles, and basic building blocks are presented. The discussion applies to most, if not all, DTCs and TDCs. A series of voltage-controlled delay units are used as the primary building block of these converter circuits. When configured in a servo-loop manner, a very short time resolution is achievable with excellent manufacturing robustness. Such designs can be synthesized in field-programmable gate arrays (FPGAs) or constructed in custom silicon. TDCs and DTCs are not new, as they have extensively been used for making very accurate and repeatable time measurements in both the physics-related and semiconductor industry. Today, TDCs and DTCs are finding new applications in phase-locked loops and frequency synthesizers.

A high-quality analog oscillator using oversampling D/A conversion techniques

This paper describes a high-quality analog oscillator for low-frequency applications, which uses a combination of over-sampling and delta-sigma modulation. With the exception of a lowpass filter and a 1-bit D/A, the proposed circuit is entirely digital, providing accurate control over the oscillation frequency and amplitude. At the core of the oscillator is a digital simulation of an LC-tank circuit consisting of two cascaded integrators. This arrangement guarantees oscillation by constraining the poles of the resonator to locations on the z-plane unit-circle, even in a finite-precision implementation. To minimize circuit complexity, the entire oscillator is operated at the oversampled rate, thereby eliminating the associated interpolation filter. Furthermore, the incorporation of a delta-sigma modulator inside the resonator loop leads to a very efficient implementation requiring only 4 multi-bit adders and a 2-input multiplexor. The desired analog signal may be recovered by lowpass filtering the 1-bit output of the delta-sigma modulator. Experiments performed thus far have indicated an effective dynamic range exceeding 80 dB. >

Log-domain filters based on LC ladder synthesis

A design method is proposed for the synthesis of linear, high-order, continuous-time filters using a unique translinear integrator circuit. Unlike previous attempts at incorporating translinear circuits into filter design, the proposed theory makes explicit use of the exponential nature of the bipolar transistor. This technique is based on the operational simulation of LC ladders. A 5th-order Chebyshev filter is designed, simulated and verified experimentally. The filter shows good amplitude response as well as distortion levels comparable to other filtering schemes.

An analog multi-tone signal generator for built-in-self-test applications

This paper presents the design of an analog oscillator capable of generating multi-tone signals by encoding the information in an oversampled delta-sigma modulated bit-stream. With the exception of an imprecise lowpass filter, the proposed design is completely digital allowing accurate control of the amplitude, frequency, and phase of all sinusoids making up the multi-tone signal. Simulations and FPGA experiments performed to date have verified the performance of the proposed design which is envisioned to open new directions in the mixed analog/digital testing field.