Mohamed Saeed

1.5–3.3 GHz, 0.0077 mm2, 7 mW All-Digital Delay-Locked Loop With Dead-Zone Free Phase Detector in

A 1.5–3.3 GHz, 7 mW, all-digital delay-locked loop (ADDLL) designed in a UMC 130-nm CMOS technology is presented in this paper. The proposed ADDLL uses the modified successive approximation register to control a NAND-based coarse delay line, which enables wider operating frequency range and small intrinsic delay. The inverter-based fine delay line is controlled by an XOR-based up/down counter with dead-zone free phase detector to overcome the dead-zone problem of conventional phase detectors. The D-type flip-flops in the phase detector are modified to detect sub-ps level delay difference between the input and output clocks, so that a delay resolution of better than 1 ps is achieved in the proposed design. The combination of both coarse and fine locking processes gives outstanding performance in terms of residual phase difference and output jitter. The overall design occupies 0.0077 mm2 area. The experimental results show that the peak-to-peak and root mean square jitters are 12 and 1.629 ps at 3.3 GHz, respectively, while the input jitter is 2.6 ps peak-to-peak and 612 fs rms.

0.13~\mu \text{m}

This paper presents the design and implementation of an integrated wideband Marchand balun in standard 65nm CMOS technology. The proposed balun operates from 16 GHz to 21 GHz achieving high coupling together with significantly low phase and amplitude imbalance between the balun outputs. A new balun structure is proposed to solve the nonideal ground problem in CMOS-based microwave circuits, and coherently enables the injection of DC signal to bias the consecutive circuits. The proposed prototype is implemented in TSMC 65nm 1P9M standard CMOS technology occupying total area of 280 μm × 310 μm, and achieves maximum phase variation of ±2°, and maximum amplitude imbalance of 2 dB which makes it suitable for wideband microwave applications.

CMOS

In this paper we report a compact, zero-biased Graphene-based power detector circuit based on our in-house metal-insulator-Graphene (MIG) diode fabricated on glass substrate. The designed circuit is optimized for the frequency band 40–75 GHz. Measurements show dynamic range of more than 50 dB with down to −50 dBm sensitivity. The measured responsivity for the fabricated circuit on glass is 168 V/W at 2.5 GHz and it reaches 15 V/W at 60 GHz without calibration for substrate losses. Measurement results together with the introduced CVD Graphene process promote the proposed circuit and device for repeatable, statistically stable millimeter-wave and sub-millimeter wave circuits applications.

Integrated, 16–21GHz Marchand balun in 65nm CMOS

This paper describes an available graphene process with respect to material properties and also the work in progress to complete the graphene process back-end implementation to be MMIC-compatible. This process extension is critical to enable fully integrated circuits and systems based on graphene transistors. A stable process back-end is proposed, characterized and tested on both silicon and quartz substrates. Based on this, a process cross-section is now available for EM simulations. A prototype chip of RF passive devices including spiral inductors, MIM capacitors and thin film resistors, TFRs, is fabricated and measured on both substrates. On-wafer measurements of the fabricated passive devices up to 30 GHz show good agreement with EM simulation results.