Ahmed Farouk Aref

A Fully Integrated Adaptive Multiband Multimode Switching-Mode CMOS Power Amplifier

This paper presents a fully integrated adaptive multiband multimode switching-mode power amplifier (SMPA) in CMOS technology. The power amplifier (PA) module, consisting of input matching, driver, output stage, load transformation network (LTN), and auxiliary circuitry, utilizes optimized driving waveforms to increase output power and efficiency of a SWPA. The PA module is packaged in a 32 quad flat no-lead package. Based on the detailed analysis on appropriate driving waveforms, the SMPA is designed to maximize its output power and efficiency with minimum on-chip harmonic terminations. Furthermore, an adaptive gain control technique is proposed to control the SMPA gain at back-off while boosting the power-added efficiency (PAE) using a fully integrated tunable LTN. Employing both techniques concurrently enables us to have a multiband multimode SMPA. Measurements on a PA module designed in 90-nm CMOS and incorporating theses findings result in peak PAE of 43% for an output power of 27.1 dBm, associated with a large-signal gain of 22.1 dB at 1.97 GHz, when the devices are biased at 2.8 V. With the tunable LTN PAE at 4- and 6-dB backoff is 30% and 23%, respectively. To our knowledge, this is the first fully integrated multiband multimode SMPA in CMOS technology.

System-level performance study of a multistandard outphasing transmitter using optimised multilevels

This paper analyses an energy-efficient multimode and multistandard LINC transmitter. This architecture is based on controlling the output power of highly efficient power amplifiers. Compared with the classical LINC, an multilevel selection algorithm is developed to optimise the levels depedent on the signal statistics in order to boost average power efficiency. Based on this algorithm, a multilevel LINC transmitter is implemented on a system-level. The architecture can be configured for different standards, such as EDGE, WCDMA and LTE. Models and algorithm are developed in SystemC and Matlab for the exploration of design specification and verification of the complete system. Simulation results show that compared with the classical LINC, average power added efficiency is improved from 10.5 % to 29.26 % for an uplink LTE signal with a peak-to-average power ratio of 6 dB. Futhermore, compared with equal-distance multilevel LINC systems, an efficiency boosting between 6 % and 0.5 % points can also be achieved for 2 to 8 multilevels.

A Study of the Impact of Delay Mismatch on Linearity of Outphasing Transmitters

This paper presents an analytical study of the impact of delay mismatch on the linearity of outphasing transmitters. Analytical expressions are derived to quantify the impact of delay mismatch between the two amplifying paths on the adjacent channel power ratio and error vector magnitude of any complex modulated output signal. These expressions can be used to specify delay mismatch for any given requirement of linearity performance of an outphasing transmitter. A complete LTE transceiver physical layer model in simulink is used to simulate the whole transceiver chain. An embedded model of an outphasing transmitter with a variable delay mismatch is included to compare error vector magnitude simulation data with theoretically derived results for different LTE downlink channels of 1.4 MHz, 10 MHz and 20 MHz channel bandwidths. Outphasing signals are synthesized with different delays and uploaded to a vector signal generator such that adjacent channel power ratios can be measured. This allows for a comparison between hardware-probed results and the theoretical calculations for LTE channels of 1.4 MHz and 10 MHz channel bandwidths.

2.6 Class-0: A highly linear class of power amplifiers in 0.13μm CMOS for WCDMA/LTE applications

Integration of RF transceiver blocks along with the digital signal processing part in CMOS is becoming the trend in the semiconductor industry for lower cost and smaller form factor. Nowadays, the interest is even growing towards implementing the RF PA in CMOS technology. Cost reduction, diversifying means of fabrication and the addition of performance enhancement circuitry are the main reasons behind this growing interest. However, implementing RF PAs for 3G/4G standards in CMOS is quite challenging: The low breakdown voltage of nanoscale CMOS causes a ruggedness problem at typical average output power (Pavg) levels of 26dBm or more. In the paper, power-combining techniques were used to reach PA output power (Pout) of 33dBm. However, amplification of signals with high peak-to-average-power-ratio (PAPR) requires also a high degree of linearity. Significant AM-PM distortions caused by the voltage-dependent parasitics are a fundamental problem in CMOS PAs. Thus far, predistortion is used to meet EVM requirements. To overcome these challenges, this work presents a new class of operation, termed as Class-O, demonstrated by the design and the measurement of a single-stage PA implemented in 0.13μm CMOS and operating from a 3.3V supply.

Improvement on linearity with iterative calibration technique for multilevel LINC transmitters

This paper proposes an iterative calibration technique to enhance the linearity for multilevel LINC transmitters. With this approach, the precision of characterising AM/AM and AM/PM behaviours for discrete levels can be improved, which results in better adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) performance. An ML-LINC transmitter is built with two PAs in GaN technology, which delivers 40.8 dBm output power with 68% drain efficiency at 2.05 GHz. Up to 5 dB ACLR improvement can be observed by iterative calibration using S1/S2 for a 5 MHz LTE signals. The configuration with 16 levels can give satisfying linearity performance to meet the standard specification, while keep the complexity reasonable. Measurement results show an ACLR of -46 dBc, EVM of 1.9% (QPSK) and 4.2% (64-QAM) at average output power of 35.7 dBm with 51.1% drain efficiency for a 10 MHz LTE signals with a PAPR of 7.9 dB. The performance of the built ML-LINC tranmitter is compared to the state-of-the-art. Both the linearity and drain efficiency are quite competitive.

Achieving linearity for outphasing amplifiers targeting LTE applications and beyond

This paper analyses the impact of the level locations in a multilevel LINC transmitter on the obtainable linearity performance. Results show that by placing levels in the upper dynamic region of outphased signals, a linearity performance suitable for LTE applications and beyond can be achieved. A multilevel LINC transmitter with 5 levels is implemented using 10 W GaN CREE devices at 1.9 GHz. A 10 dB PAPR 1.4 MHz LTE signal is decomposed for outphasing and recombined to achieve an ACPR performance of -50 dBc while delivering 2 W average output power.

Impact of the number of levels on the performance of multilevel LINC transmitters

This paper analyses an energy-efficient multilevel LINC transmitter with low complexity. Compared with a conventional multilevel LINC using a supply modulator, a new architecture to realise multiple levels is analysed. With this architecture, distortion caused by delay mismatch and memory effects caused by the limited bandwidth of PAs can be mitigated resulting in improved out-of-band emissions. A system analysis shows the improvement of performance regarding efficiency, spectrum and ACLR in presence of delay mismatch and system bandwidth limitations. The analysis at system level is verified by measurements complying with 3GPP LTE specification. An improvement of 17 dB in out-of-band emission is observed by increasing the number of levels from 1 to 40. Meanwhile, average efficiency is also increased from 12 % to 42 %.

Analysis of design specification for digital polar RF transmitter at system and architectural level

The polar transmitter is an alternative RF transmitter architecture solution for highly efficient amplification of nonconstant envelope signals. This paper presents an analysis of system performance of digital polar RF transmitters. The approach is to analyse the relation between error vector magnitude (EVM) and output power spectrum density (PSD). The requirements on amplitude dynamic range, bit resolution and time delay mismatch for AM/PM paths are studied and used to specify the design of digital polar RF transmitters. All the components in the digital polar RF transmitter have been modelled both in Matlab and SystemC. The analysis and simulation can be completed within seconds. Based upon the presented analysis results, optimum design parameters for the components and system can be easily derived. With the analysed specification, the performance of the polar transmitter regarding EVM and PSD is verified at the system level as well.

1.5–3.3 GHz, 0.0077 mm2, 7 mW All-Digital Delay-Locked Loop With Dead-Zone Free Phase Detector in

A 1.5–3.3 GHz, 7 mW, all-digital delay-locked loop (ADDLL) designed in a UMC 130-nm CMOS technology is presented in this paper. The proposed ADDLL uses the modified successive approximation register to control a NAND-based coarse delay line, which enables wider operating frequency range and small intrinsic delay. The inverter-based fine delay line is controlled by an XOR-based up/down counter with dead-zone free phase detector to overcome the dead-zone problem of conventional phase detectors. The D-type flip-flops in the phase detector are modified to detect sub-ps level delay difference between the input and output clocks, so that a delay resolution of better than 1 ps is achieved in the proposed design. The combination of both coarse and fine locking processes gives outstanding performance in terms of residual phase difference and output jitter. The overall design occupies 0.0077 mm2 area. The experimental results show that the peak-to-peak and root mean square jitters are 12 and 1.629 ps at 3.3 GHz, respectively, while the input jitter is 2.6 ps peak-to-peak and 612 fs rms.

0.13~\mu \text{m}

This paper presents a highly linear low-band 706MHz LTE compatible class-O RF power amplifier in 130nm CMOS technology for handheld wireless applications. Class-O topology uses a combination of common-source and common-drain amplifiers working in parallel with high linearity without the need for digital predistortion(DPD). With continuous wave measurements, 1-dB compression point (P1dB) of 30.6dBm and peak power added efficiency (PAE) of 45.2% is achieved. For the modulated signal measurements, the amplifier is tested with 16-QAM 20MHz LTE signal with peak-to-average-power ratio of 6.54 dB. The amplifier meets the stringent LTE specs with an ACPR less than -30 dBc for both EUTRA and UTRA1 with average output power of 27 dBm and PAE above 20%. Owing to the voltage following between gate source junctions in the common-drain amplifier in addition to cascode structure of common-source amplifier, the stress is significantly reduced at the transistor terminals. The reliability is demonstrated by operating the amplifier in nominal and worst VSWR conditions.