Mohammad Ayoub Khan

Handbook of Research on Industrial Informatics and Manufacturing Intelligence: Innovations and Solutions

As industrial systems become more widespread, they are quickly becoming network-enabled, and their behavior is becoming more complex and intelligent. The Handbook of Research on Industrial Informatics and Manufacturing Intelligence: Innovations and Solutions is the best source for the most current, relevant, cutting-edge research in the field of industrial informatics. The book focuses on different methodologies of information technologies to enhance industrial fabrication, intelligence, and manufacturing processes. Industrial informatics uses the infrastructure of information technology for analysis, effectiveness, reliability, higher efficiency, security enhancement in the industrial environment, and this book collects the latest publications relevant to academics and practitioners alike.

Design of 8-Bit Programmable Crossbar Switch for Network-on-Chip Router

The Network-on-Chip (NoC) uses multiple processors, usually targeted for embedded applications. This is widely accepted that NoC represents a promising solution for forthcoming complex embedded systems. The current SoC Solutions are built from heterogeneous hardware and Software components integrated around a complex communication infrastructure. The crossbar is a vital component of in any NoC router. The crossbar allocates requested output channel. Hence, switches must include an efficient arbiter that allocates crossbar’s resources(channel). In this paper, we present a novel 8-bit wide 8 x 8 crossbar that is implemented on FPGA. This high performance crossbar is coined with Diagonal Propagation Arbiter (DPA). The presented crossbar requires a two-dimensional arbitration that incorporates a diagonally rotated priority to provide fair arbitration. The arbiter is capable of performing arbitration in 1ns on Vertex 6 FPGA technology for an 8 x 8 crossbar. The proposed architecture of crossbar is implemented in RTL model using verilog language.

Business Strategies and Approaches for Effective Engineering Management

Saqib Saeed is an assistant professor at the Computer Science department at Bahria University Islamabad, Pakistan. He has a Ph.D.in Information Systems from University of Siegen, Germany, and a Masters degree in Software Technology from Stuttgart University of Applied Sciences, Germany. He is also a certified software quality engineer from American Society of Quality. His research interests lie in the areas of human centered computing, computer supported cooperative work, and empirical software engineering and ICT4D. Saqib Saeed (Bahria University Islamabad, Pakistan), Mohammad Ayoub Khan (Centre for Development of Advanced Computing, India) and Rizwan Ahmad (Qatar University, Qatar)

Area-efficient programmable arbiter for inter-layer communications in 3-D network-on-chip

The Network-on-Chip (NoC) is an emerging communication technique for System-on-Chip (SoC) communications. The NoC uses multiple processors, usually targeted for embedded applications and other applications [3, 13]. Performance of the bus is degraded by the increasing number of processing elements and transaction oriented model [13]. This has attracted much attention for applying wireless network protocols as CDMA, TDMA, and dTDMA in SoC. The TDMA systems use a fixed number of timeslots. This protocol wastes bandwidth when some timeslots are allocated but not used. The dynamic TDMA (dTDMA) bus arbiter dynamically grows and shrinks the number of timeslots to match the number of active transmitters [14]. In this paper, we present a design of area-efficient switch for inter-layer communications in 3-D NoC. The arbitration logic in the switch is based on a programmable priority encoder. A 640-bit message with uniform random destination data pattern was injected per IP per machine clock cycle. We have obtained the maximum clock frequency of 2.09 GHz for 96(4 × 8 × 3) IP cores connected in a mesh topology. The presented architecture demonstrates their superior functionality in terms of speed, latency, area, and power consumption as compared with the existing implementation [14]. The maximum power consumption of the proposed area-efficient programmable arbiter is 0.625 mW. The design is synthesized using 180nm TSMC Technology.

Embedded and real time system development : a software engineering perspective

Nowadays embedded and real-time systems contain complex software. The complexity of embedded systems is increasing, and the amount and variety of software in the embedded products are growing. This creates a big challenge for embedded and real-time software development processes and there is a need to developseparatemetrics and benchmarks. Embedded and Real Time System Development: A Software Engineering Perspective: Concepts, Methods and Principles presents practical as well as conceptual knowledge of the latest tools, techniques and methodologies of embedded software engineering and real-time systems. Each chapter includes an in-depth investigation regarding the actual or potential role of software engineering tools in the context of the embedded system and real-time system. The book presents state-of-the art and future perspectives with industry experts, researchers, and academicians sharing ideas and experiences including surrounding frontier technologies, breakthroughs, innovative solutions and applications. The book is organized into four parts Embedded Software Development Process, Design Patterns and Development Methodology, Modelling Framework and Performance Analysis, Power Management and Deployment with altogether 12 chapters. The book is aiming at (i) undergraduate students and postgraduate students conducting research in the areas of embedded software engineering and real-time systems; (ii) researchers at universities and other institutions working in these fields; and (iii) practitioners in the R&D departments of embedded system. It can be used as an advanced reference for a course taught at the postgraduate level in embedded software engineering and real-time systems.

Standard test bench for optimization and characterization of combinational circuits

Choice of a combinational circuit among large number of circuits having same functionality has been always a complex and time consuming task for digital designers. Different circuits (where they are initially proposed) were optimized using different techniques and objectives. Moreover there merits vary as per optimization methodology and technique variations. Hence every time when there is a requirement of particular functionality circuit, choosing best one amongst available circuits requires re-characterization. The paper presents a thorough investigation of existing optimization techniques while presenting their merits and demerits over each other. Based on same, the paper proposes a standard test bench for optimization and characterization of combinational circuits. Finally using the proposed methodology a combinational circuitry has been successfully characterized.