Kunwar Singh

An Area and Power Efficient Design of Single Edge Triggered D-Flip Flop

In this paper, a single edge-triggered, static D flip-flop design suitable, for low power and low area requirements is proposed. Advantageously, the flip-flop is realized using only ten transistors. The flip-flop is implemented using Master-Slave configuration and can be used for lower cost memory and microprocessor chips. The 0.6-micron technology is used to implement the design and the area and power results were compared with existing SET D FFs. Simulation results indicated that the circuit is capable of significant power savings.

A modified implementation of tristate inverter based static master-slave flip-flop with improved power-delay-area product.

The paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density. Based on the proposed structure, traditional C2MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The modified C2MOS based flip-flop designs mC2MOSff1 and mC2MOSff2 are realized using only sixteen transistors each while the number of clocked transistors is also reduced in case of mC2MOSff1. Postlayout simulations indicate that mC2MOSff1 flip-flop shows 12.4% improvement in PDAP (power-delay-area product) when compared with transmission gate flip-flop (TGFF) at 16X capacitive load which is considered to be the best design alternative among the conventional master-slave flip-flops. To validate the correct behaviour of the proposed design, an eight bit asynchronous counter is designed to layout level. LVS and parasitic extraction were carried out on Calibre, whereas layouts were implemented using IC station (Mentor Graphics). HSPICE simulations were used to characterize the transient response of the flip-flop designs in a 180 nm/1.8 V CMOS technology. Simulations were also performed at 130 nm, 90 nm, and 65 nm to reveal the scalability of both the designs at modern process nodes.

A novel methodology for flip-flop optimization and characterization in NOC design space

The paper proposes a new methodology for optimization and characterization of flip-flops that can be utilized in designing EDA tool for NOC. In automated RTL to GDS II design space there is requirement of libraries with large number of cells. Now each design can have large number of different driving strength cells. Hence the paper proposes a methodology by virtue of which the library size can be reduced while reducing complexity. The proposed approach utilizes Levenberg-Marquardt (LM) algorithm embedded in SPICE. The optimization and characterization process is entirely automated which can dramatically reduce the time required for digital integrated circuit design process. Moreover, a new flip-flop for low noise environment is proposed and compared with benchmark flip-flops using the proposed methodology. To obtain the relative performance of proposed designs with in specified design constraints, extensive spice simulations were performed using 180nm technology with BSIM 3v3 parameters and 250MHz clock frequency. The automated layouts were also generated and post layout simulation with RC extraction were executed using Mentor Graphics tool.

Logical effort based automated transistor width optimization methodology

The paper presents a new automated transistor width optimization methodology for SoC. The methodology is based on Logical Effort theory. The proposed methodology is completely automation based and uses different procedural blocks written in TCL (tool command language). The methodology requires SPICE netlist as input and optimizes transistor widths for minimum delay. Both sequential (flip-flop) and combinational (basic logic gates) logic blocks were optimized successfully using the proposed methodology.

Automated transistor width optimisation algorithms for digital circuits

This paper presents two novel automated transistor width optimisation algorithms based on Levenberg-Marquardt (LM) algorithm (embedded in SPICE) and logical effort theory proposed by Sutherland et al. (2004). This paper has incorporated the complete logical effort theory from scratch in TCL; hence, it works independent of SPICE tool and can optimise any number of transistors present in circuit. The algorithm can be used as open source optimisation tool and modifications can be done to it according to the need. The proposed algorithms can be utilised for automated library cell characterisation where precise and large numbers of driving strength cells are required. Since the algorithms are automation based, they can play a pivotal role in development of library less synthesis. Optimisations results using proposed algorithms were obtained for both sequential logic blocks (flip-flop) and combinational logic blocks (basic logic gates). Both the algorithms have their own advantages and disadvantages.

Standard test bench for optimization and characterization of combinational circuits

Choice of a combinational circuit among large number of circuits having same functionality has been always a complex and time consuming task for digital designers. Different circuits (where they are initially proposed) were optimized using different techniques and objectives. Moreover there merits vary as per optimization methodology and technique variations. Hence every time when there is a requirement of particular functionality circuit, choosing best one amongst available circuits requires re-characterization. The paper presents a thorough investigation of existing optimization techniques while presenting their merits and demerits over each other. Based on same, the paper proposes a standard test bench for optimization and characterization of combinational circuits. Finally using the proposed methodology a combinational circuitry has been successfully characterized.

Design and development of circuit optimizer using TCl and SPECTREMDL(SPICE) interface

Digital and analog designers are always interested in automated optimization of transistor width values for customized requirements. SPICE tools are now embedded with certain options [like L-M algorithm and parametric analysis] by virtue of which automated width optimization can be performed upto a certain extent. Whereas when the optimization requirements are very specific they seem to be helpless. For customization of automation process several research had been done in past, of them the most valuable being the PSPICE and MATLAB interface. Since PSPICE has its own limitation, hence the horizon of the interface is limited. The paper proposes a novel circuit optimizer using TCL and SPECTREMDL interface. Hence, instead of using only the algorithms embedded in SPICE tools, the designer has a flexibility to write new algorithms in TCL and analyze the circuit behavior with the interface, while having the flexibility to re-optimize the circuit again and again by changing the input values with the help of designed algorithm. The interface between TCL and SPECTREMDL has been demonstrated by applying the methodology to standard Flip-Flop circuits.