Mohammad Fawaz

Redundancy-aware electromigration checking for mesh power grids

Electromigration (EM) is re-emerging as a significant problem in modern integrated circuits (IC). Especially in power grids, due to shrinking wire widths and increasing current densities, there is little or no margin left between the predicted EM stress and that allowed by the EM design rules. Statistical Electromigration Budgeting (SEB) estimates the reliability of the grid by considering it entirely as a series system. However, a power grid with its many parallel paths has much inherent redundancy. In this paper, we propose a new model to estimate the MTF and reliability of the power grid under the influence of EM, which accounts for these redundancies. We refer to this as the mesh model. To implement the mesh model, we also develop a framework to estimate the change in statistics of an interconnect as its effective-EM current varies. The proposed algorithm is quite fast and has an overall observed empirical complexity of 0(n1.4). The results indicate that the series model, which is currently used in the industry, gives a pessimistic estimate of power grid MTF and reliability by a factor of 3-4.

FPGA-based Internet protocol firewall chip

We present the design of a firewall for IP networks using a field-programmable gate array (FPGA). The FPGA implements, in hardware, the accept or deny rules of the firewall. A hardware-based firewall offers the advantages of speed over a software firewall, in addition to direct interfacing with network devices, such as an Ethernet or a serial line transceiver. This paper shows how the rules are translated to VHDL and then implemented in hardware, and how the hardware is utilized to filter network traffic in a packet-by-packet fashion, or based on connection information, with a speed of more than 500,000 packets per second.

Accurate verification of RC power grids

The power distribution network (PDN) of an integrated circuit (IC) must undergo various checks throughout the design flow, in order to guarantee that the voltage fluctuations are within certain user-specified safety thresholds. Vectorless verification of the PDN is one approach for verification that requires little information about the on-die logic. This verification problem has been studied extensively over the past few years and has been generally solved by first discretizing time using a particular user-defined time-step. We investigate the effect of this time-step on the quality of the solutions produced (both exact and estimates). We also propose an efficient method to specify the time-step in a way to minimize the errors introduced by the voltage drop estimates.

A vectorless framework for power grid electromigration checking

Electromigration (EM) in the on-die metal lines has re-emerged as a significant concern in modern VLSI circuits. The higher levels of temperature on die and the very large number of metal lines, coupled with the conservatism inherent in traditional EM checking strategies, have led to a situation where trying to guarantee EM reliability often leads to unacceptably conservative designs that may not meet the area or performance specs. Due to unidirectional currents, this problem is most significant in the power and ground grids. Thus, this work is aimed at reducing the pessimism in EM prediction for power/ground grids. There are two sources for the high pessimism: 1) the use of the traditional series model for EM checking and 2) pessimistic assumptions about the chip workload and the corresponding supply currents. To address this problem, we propose a framework for EM checking that allows users to specify conditions-of-use type constraints that help capture realistic chip workload and which includes the use of a novel mesh model for EM prediction in the grid, instead of the traditional series model.

Fast Vectorless RLC Grid Verification

Checking the power distribution network of an integrated circuit must start early in the design process, when changes to the grid can be more easily implemented. Vectorless verification is a technique that achieves this goal by demanding limited information about the currents drawn from the grid. State of the art techniques that deal with RLC grids become prohibitive even for medium size grids. In this paper, we propose a novel technique that estimates the worst-case voltage fluctuations for RLC grids by carefully selecting the time step, in a way that significantly reduces the number of linear programs that need to be solved, and eliminates the need for other expensive computations, like dense matrix-matrix multiplications. Results show that our technique is accurate and scalable for large grids as it achieves over

Fast simulation-based verification of RC power grids

19{\times }

Testing techniques for resistive-open defects in future CMOS technologies

speedup over existing methods.

Parallel Simulation-Based Verification of RC Power Grids

To guarantee its safety, the power delivery network (PDN) must undergo a sequence of verification steps throughout the integrated circuit (IC) design flow. This involves checking that the voltage fluctuations in the grid remain within some user-specified safety threshold. Typically, this is done by performing a transient simulation of the grid under certain input current traces. Existing simulation tools require solving a large number of linear systems, making the tools slow for modern power grids containing billions of nodes. We propose a new simulation based approach for RC power grid verification that generates envelope upper bound waveforms on the true voltage drop waveforms. The envelope waveforms capture the peaks of the voltage drops quite accurately while requiring a much smaller number of system solves than traditional tools.

Transient current and delay analysis for resistive-open defects in future 16 nm CMOS circuits

In this paper, we investigate the effectiveness of different testing techniques in detecting resistive-open defects for adder circuits implemented using current and future CMOS technologies down to 22nm. We take into consideration the wide process variations associated with such technologies. The first method is based on monitoring various characteristics of the transient power supply and ground currents (iDDT) while the second method relies on measuring the propagation delay from the primary inputs to primary outputs. The transistor models are acquired from the Predictive Technology Model website (PTM) and the percentage variations for technology parameters are obtained from the existing literature. Results show the effectiveness of the iDDT methods for small circuits. However, the capability of the method declines for larger circuits. The delay test proves to be very effective in all cases.

Redundancy-Aware Power Grid Electromigration Checking Under Workload Uncertainties

The power delivery network (PDN) must undergo a sequence of verification steps throughout the integrated circuit (IC) design flow. Typically, this is done by performing a transient simulation of the grid under certain input current traces, and checking that the resulting node voltages are within some user-specified thresholds. Existing tools require solving a large number of linear systems making them slow for modern power grids with billions of nodes. We propose a parallel simulation-based tool for RC grid verification that generates envelope waveforms on the true voltage drop waveforms. The resulting waveforms capture the peaks of the voltage drops quite accurately and require solving a much smaller number of linear systems than traditional tools.