Gh. Mohammad

Flash memory disturbances: modeling and test

Nonvolatile Memories (NVMs) can undergo different types of disturbances. These disturbances are particular to the technology and the cell structure of the memory element. In this paper we develop a coupling fault model that appropriately models disturbances in flash memories that use floating gate transistor as their core memory element. We describe the behavior of faulty cells under different fault models and how their characteristics change under each model. We demonstrate the inappropriateness of conventional march algorithms for testing flash memories and present a procedure to derive pseudo-algorithms that can be used in testing flash memories. In addition we present an efficient test that detects these disturbances under different fault models developed in this paper.

Simulating program disturb faults in flash memories using SPICE compatible electrical model

Electrical simulation is an important tool that enables designers to evaluate different design alternatives and assess their performance. In memory technology, these tools are used to study the performance of different cell structures and implementations. In this paper we use such simulations to study the impact of defects on the performance of flash memory bitcells. In particular, using a device level simulator, we develop a SPICE compatible model to simulate the operation of a 1T flash bitcell. We then describe a fault injection technique that can be used, in conjunction with the model, to simulate faulty cell behavior. The model is used to simulate different defects in the oxide layer of the flash core memory element. The impact of defects on bitcell behavior under disturb and normal operations is investigated and evaluated. The model is demonstrated to be valuable to evaluate the appropriateness of the logic tests and stress tests used to detect such defects in flash memories.

Fault Models and Test Procedures for Flash Memory Disturbances

Disturbances are special type of faults that are unique to flash memories. Causes of the disturbances are defects within the insulating layers of the memory element. These defects result in abnormal behavior of a memory cell under specific conditions. This paper describes characteristics of these defects as well as their manifestation as DC-Programming, DC-Erasure, and Drain Disturbance. We develop fault models to capture the behavior of faulty flash memories. We introduce three different fault models based on the underlying defects in a memory cell. These models are: Simple, Exclusive and General Fault model. Further, we develop test algorithms that detect disturbance faults under each of the fault models. The test algorithms reported in this paper for the simple fault model for each type of disturbance require optimal number of program, read, and flash operations; where as the algorithms for the remaining two fault models require near optimal number of these operations.

Broadcast scheduling in packet radio networks using Harmony Search algorithm

Packet radio networks have attracted many applications due to their flexible structure and ability to provide high-speed wireless communication between nodes distributed over a large region. Broadcast scheduling is commonly used to find a collision-free time division multiple access protocol frame that schedule transmissions for all nodes in a minimal number of timeslots with maximum number of transmissions. In this paper, we propose a Harmony Search (HS) based algorithm for the broadcast scheduling problem. The HS-based algorithm explores the search space effectively and efficiently by exploiting the search rules of randomness, experience, and variation of experience. The effectiveness and robustness of our proposed algorithm is demonstrated through solving a set of benchmark problems and comparing the results with previously proposed techniques. Experimental results show the efficiency of the proposed algorithm in terms of quality of the solutions as well as computational time.

Frequency assignment problem in satellite communications using differential evolution

Satellite communications technology has a tremendous impact in refining our world. The frequency assignment problem is of a fundamental importance when it comes to providing high-quality transmissions in satellite communication systems. The NP-complete frequency assignment problem in satellite communications involves the rearrangement of frequencies of one set of carriers while keeping the other set fixed in order to minimize the largest and total interference among carriers. In this paper, we present a number of algorithms, based on differential evolution, to solve the frequency assignment problem. We investigate several schemes ranging from adaptive differential evolution to hybrid algorithms in which heuristic is embedded within differential evolution. The effectiveness and robustness of our proposed algorithms is demonstrated through solving a set of benchmark problems and comparing the results with a number of previously proposed techniques that solve the same problem. Experimental results show that our proposed algorithms, in general, and hybrid ones in particular, outperform the existing algorithms both in terms of the quality of the solutions and computational time.

Electrical model for program disturb faults in non-volatile memories

Non-volatile memories (NVMs) are susceptible to special type of faults known as disturb faults. A class of these disturb faults are faults induced by high electric field stress known as program disturbs. In this paper we discuss the physical nature of the defects that are responsible for these faults in flash memories. We develop an electrical fault model for defects and simulate faulty cell behavior based on physical defect location (in gate oxide). We also evaluate the impact of these defects on cell performance. The modeling technique is flexible and applicable under different disturb conditions and defect characteristics.

Phase change memory faults

Chalcogenide based phase change memory (PCM) is a promising type of non-volatile memory that possibly replace the currently wide spread flash memory. Current research on PCMs targets the integration, feasibility, and reliability of such memory technology into the widely used CMOS process technology. Such studies identified special failure modes, known as disturbs, that could occur in PCMs. In this paper, we identify these failures and analyze their defective behaviors. Moreover, we develop fault models for such disturbs in addition to faults caused by opens and shorts in the core memory cell. Further, we propose an efficient test algorithm, called March-PC, to detect all faults discussed in this work.

Fault model and test procedure for phase change memory

Chalcogenide-based phase change memory (PCM) is a type of non-volatile memory that will most likely replace the currently widespread flash memory. Current research on PCM targets the integration feasibility, as well as the reliability of such memory technology into the currently used complementary metal oxide semiconductor (CMOS) process. Such studies identified special failure modes, known as disturbs, as well as other PCM specific faults. In this study, the authors identify these failures, analyse their behaviours and develop fault primitives/models that describe these faults accurately and effectively. In addition, the authors propose an efficient test algorithm, called March-PCM, to test for these faults and compare its performance to some previously developed test algorithms.

Fault collapsing for flash memory disturb faults

Disturb failures are considered the most predominant failure mode in flash memories. Disturb faults are highly dependant on the core memory cell structure, manufacturing technology, and array organization and operation. In this paper, we develop appropriate fault primitives for all possible disturb faults in flash memories. Further, we analyze the origins of such disturbs and propose a method that uses cell structure and array organization information to identify the relevant disturbs to create reduced list of faults. As an example, the method was used to create a minimized faults list for NOR and NAND flash memory arrays. Moreover, we show how the reduced fault list developed can be used to devise more efficient test algorithms.

Testing Flash Memories for Tunnel Oxide Defects

Testing non volatile memories for tunnel oxide defects is one of the most important aspects to guarantee cell reliability. Defective tunnel oxide layer in core memory cells can result in various disturb faults. In this paper, we study various defects in the insulating layers of a IT flash cell and analyze their impact on cell performance. Further, we present a test methodology and test algorithms that enable the detection of tunnel oxide defects in an efficient manner.