Mohammed Niamat

Collabra: A Xen Hypervisor Based Collaborative Intrusion Detection System

In this paper, we introduce Collabra, a distributed intrusion detection platform based on Xen hyper visors to maintain the security of the cloud based on virtualized network. While the concept of virtual machine monitor (VMM) signifies implementing an abstraction layer between the underlying host and the guest operating system (OS) to enforce security, its kernel is required to be free of vulnerabilities that intruders can use to compromise the host. In Xen, guest applications make resource requests through the hyper-call API to transfer the privilege to the VMM kernel for executing privileged operations. On a cloud scale, there exist hundreds of VM networks and thousands of guest operating systems (OSes) running on virtual domains. There is every possibility of intruders trying to misuse the hyper-call interface to compromise guest OS kernels and finally the host OS kernel itself. Sophisticated attacks can be launched in the distributed and collaborative style thereby bypassing most current intrusion detection systems. Collabra acts as a filtering layer which is completely integrated with every VMM. It scans through each call by incorporating integrity checking and collaborative detection mechanisms. It exists in multiple instances, and acts concurrently over a VMM network interacting with other instances to detect (possibly collaborative) attacks and prevent illicit access to the VMM and the host. An admin version of Collabra exists on a privileged domain in the VM network to perform filtering of malicious add-ons to hyper-calls at the guest OS level itself before routing the call to the VMM.

Modeling impact of bypass diodes on photovoltaic cell performance under partial shading

Partial shading across solar cells can cause large reverse voltages and reduce the maximum generated output power. The effects of shading can be mitigated via the use of bypass diodes across the shaded cells. The impact of using bypass diodes on the solar cell performance under shading has been studied at a module level using MATLAB. Algorithms have been designed to study the effects of non-overlapping bypass diode configuration in a randomly shaded solar module and results have been compared with modules devoid of bypass diodes. I-V and P-V curves have been plotted and maximum peak power is tracked for severe to intermediate levels of shading patterns.

QCA design and implementation of SRAM based FPGA Configurable Logic Block

This paper presents the design and simulation of a Configurable Logic Block (CLB) using the Quantum-Dot Cellular Automata (QCA) technology. The modeling, implementation, and successful simulation of a CLB slice for a nano quantum FPGA are discussed. We have drawn comparisons with various FPGA architectures at the quantum level and optimized the proposed architecture with respect to area and latency. The design is modeled using standard QCA cells with multiple layers for reliable interconnect crossovers. The design of the CLB is implemented and simulated using the QCA Designer software tool.

FPGA implementation of the ray tracing algorithm used in the XPATCH software

Ray tracing is one of the most popular and powerful image synthesis technique for creating photo-realistic images. In this research, we focus on the time critical application of ray tracing in the XPATCH software for high-resolution radar simulation and detection. Of particular interest to us is the ray/box intersection algorithm employed in the XPATCH ray tracer for achieving faster execution time. The ray/box algorithm is used to determine whether a ray hits or misses the target enclosed in a rectangular bounded volume.

Minimal majority gate mapping of 4-variable functions for quantum cellular automata

Three-input majority gates and inverters form the basic Boolean primitive logic blocks of quantum cellular automata (QCA) circuits. Ideally, an optimized QCA design should have minimal number of gate counts and logic levels. However, existing majority gate logic synthesis methods based on three-feasible networks often result in inefficient use of majority logic gates. In this paper, we propose an improved majority gate logic synthesis technique and present a total of 143 four-variable standard functions and their majority gate implementations. These functions can be incorporated in the majority gate synthesis tools giving more efficient logic implementations. For the 13 MCNC benchmarks presented in this paper, the proposed approach yields a combined reduction of 16.2% in the number of gate counts and 5.21% in the number of levels when compared with the existing method.

A BIST scheme for testing the interconnects of SRAM-based FPGAs

This paper discusses a new testing scheme for testing the interconnect resources in the Xilinx XC4000 series field programmable gate arrays (FPGAs). The scheme is based on the concept of built in self test (BIST), which subdivides the test problem into a test pattern generator (TPG), a circuit under test (CUT) and an output response analyzer (ORA). The research involves the location and detection of single-stuck-at and bridging and open faults that might be present in the interconnect network. The test responses obtained at the output of the ORA are stored in the look up table (LUT) of the configurable logic block (CLB) so that the faulty interconnect can be detected and located. This testing scheme ensures high reliability, increased fault tolerance capacity and provides maximal fault coverage. Reduced system time, zero circuit overhead and unity test resolution are some of the highlights of this new testing scheme.

Testing FPGAs using JBits RTP cores

In this paper, we present a fault-testing technique for field programmable gate arrays (FPGAs) that is based on the features offered by Java Bits (JBits). Our technique can detect single and multiple stuck at faults, and is capable of detecting the faulty CLB within the FPGA. The algorithm proposed for testing the faults in the CLB utilizes the unified-library primitives and the run-time parameterizable (RTP) cores of the JBits programming language. The method also explores the object-oriented approach of the Java programming language used in JBits. It has the capability of providing run-time fault avoidance in FPGAs based on the faults detected during the testing process. Since JBits involves programming directly at the bitstream level, the proposed method offers additional advantages over traditional testing techniques

Logic BIST architecture for FPGAs

In this paper, we propose a built-in-self-test (BIST) based approach for testing the configurable logic blocks of FPGAs. BIST technique, when applied to a FPGA, does not need any additional testing circuitry. BIST logic is programmed into the FPGA in test mode and the FPGA is reprogrammed to perform its normal function once testing is completed. This effectively eliminates the need for any additional design-for-test circuitry.

Analyzing the performance of a configurable ROPUF design controlled by programmable XOR gates

Physical unclonable functions (PUFs), are physical entities that are embodied in a silicon chips and can be easily evaluated but they are difficult to predict. Ring Oscillators (ROPUFs) are appropriate security techniques for FPGA-based systems. This paper presents a Configurable design of ROPUF controlled with programmable XOR (PXORs) gates for area efficiency and stronger secret key production. PXORs gates are integrated in our design in order to control the frequencies of the Ring Oscillators. The proposed design is mapped on the entire area of five Xilinx Spartan-3E FPGAs, and takes advantage of the dedicated logic in the Configurable Logic Blocks (CLBs) to create multiple ROs. The Experimental results show that the design presented exhibits high performance in terms of average RO frequencies, average RO standard deviation, and a static variation ratio which is considerably higher than the dynamic variation. In addition, an efficient algorithm to reduce systematic variations and improve ROPUF uniqueness is presented.

Analysis of photovoltaic array with reconfigurable modules under partial shading

Partial shading across solar arrays can significantly deteriorate maximum generated power. Typical arrays implementing a parallel-in-series architecture have bypass diodes integrated in the modules to reduce the effects of partial shading. In this paper, analysis is performed on the effectiveness of improving maximum power of a solar array comprising of modules and reconfigurable switches. Matlab models are developed for modules with and without bypass diodes. I-V and P-V curves are simulated for several shading patterns. Significant improvement in the fill factors has been observed when using reconfigurable switches. The absence of reconfigurable switches reduced the peak power by almost 88% under some partial shading scenarios.