Srinivasa Vemuru

Modeling impact of bypass diodes on photovoltaic cell performance under partial shading

Partial shading across solar cells can cause large reverse voltages and reduce the maximum generated output power. The effects of shading can be mitigated via the use of bypass diodes across the shaded cells. The impact of using bypass diodes on the solar cell performance under shading has been studied at a module level using MATLAB. Algorithms have been designed to study the effects of non-overlapping bypass diode configuration in a randomly shaded solar module and results have been compared with modules devoid of bypass diodes. I-V and P-V curves have been plotted and maximum peak power is tracked for severe to intermediate levels of shading patterns.

Minimal majority gate mapping of 4-variable functions for quantum cellular automata

Three-input majority gates and inverters form the basic Boolean primitive logic blocks of quantum cellular automata (QCA) circuits. Ideally, an optimized QCA design should have minimal number of gate counts and logic levels. However, existing majority gate logic synthesis methods based on three-feasible networks often result in inefficient use of majority logic gates. In this paper, we propose an improved majority gate logic synthesis technique and present a total of 143 four-variable standard functions and their majority gate implementations. These functions can be incorporated in the majority gate synthesis tools giving more efficient logic implementations. For the 13 MCNC benchmarks presented in this paper, the proposed approach yields a combined reduction of 16.2% in the number of gate counts and 5.21% in the number of levels when compared with the existing method.

Bus encoding scheme to eliminate unwanted signal transitions

As the technology scales down, the increased wire aspect ratio and the reduced spacing between the individual wires within a bus result in increased cross-coupling capacitances. This increases crosstalk noise and power dissipation particularly in wide data buses. We propose an efficient encoding scheme that eliminates correlated switching (coupling transitions) in 4-bit buses and also minimizes self-transitions among the wires in these data busses. Wider data busses are implemented using these 4-bit bus blocks.

Small signal modeling of diode in a parallel module subjected to partial shading

Parallel connection of solar cells results in a very small difference in the internal p-n junction voltages when operated under partial shaded conditions. A small signal model is proposed in this paper to analyze the changes in the module parameters of parallel cells operating under this conditions. From the analysis it is observed that the maximum power for a parallel configured solar module is obtained at a fixed output resistance under varied shaded conditions. Circuit simulations validated the model implemented in Matlab.

Analysis of photovoltaic array with reconfigurable modules under partial shading

Partial shading across solar arrays can significantly deteriorate maximum generated power. Typical arrays implementing a parallel-in-series architecture have bypass diodes integrated in the modules to reduce the effects of partial shading. In this paper, analysis is performed on the effectiveness of improving maximum power of a solar array comprising of modules and reconfigurable switches. Matlab models are developed for modules with and without bypass diodes. I-V and P-V curves are simulated for several shading patterns. Significant improvement in the fill factors has been observed when using reconfigurable switches. The absence of reconfigurable switches reduced the peak power by almost 88% under some partial shading scenarios.

Synthesis of Majority/Minority Logic Networks

As CMOS technology reaches its physical limits, new technologies such as quantum-dot cellular automata, single electron tunneling, and tunneling-phase logic are being proposed as alternatives to CMOS technology. These technologies use either majority or minority logic to implement logic functions. Existing majority/minority logic synthesis methods, based on three-feasible networks, often result in suboptimal solutions. In this paper, an efficient algorithm to find the minimal majority gate mapping, along with a majority expression look-up table (MLUT) is developed. Based on the MLUT, a comprehensive majority/minority logic synthesis technique is proposed. A redundancy removal method is also developed to further optimize the synthesized circuit. This technique makes effort toward achieving different optimization goals and results in fewer majority gates and fewer levels than previous methods. For the 29 MCNC benchmark circuits, when targeted to optimize the logic levels, there is an average reduction of 7.0% in the number of levels as well as 6.3% in the number of gates. For optimization targeted to reduce gate counts, there is an average reduction of 9.5% in the number of gates as well as 0.8% in the number of levels, as compared to the best available method.

Comparison of multilevel DC-DC converter topologies

Multilevel DC-DC converter systems are used to transform low level DC voltages to larger DC voltages. Different topologies of multilevel DC-DC power converters such as cascaded model, one-to-many model and general multilevel DC-DC converter modules are studied and compared. These topologies are compared in terms of the number of discrete steps of output voltage levels, number of switching elements, and the ease of converting between different voltage levels.

Modeling of Random Shading Effects in Solar Cells

This paper introduces a modeling scheme that takes the effects of shading patterns on the output power of a solar cell array using MATLAB. A module consisting of an array of parallel connected strings of solar cells is considered for analysis under shading conditions. The model finds the solutions of complex nonlinear equations of solar cell under random illumination conditions. The approach has been extended to special shading cases. Additionally the effect of load resistance variation on the maximum power point under different shading patterns is performed.

Comprehensive majority/minority logic synthesis method

New technologies such as Quantum-dot Cellular Automata (QCA), Single Electron Tunneling (SET) and Tunneling Phase Logic (TPL) have been proposed as alternatives for CMOS technology. These technologies are based on the use of majority/minority logic. Existing logic synthesis methods targeting majority/minority logic based on three-feasible networks often result in non-optimal solutions. In this paper, we propose an improved synthesis technique that can process three-feasible and four-feasible networks. A method for finding the minimal majority expressions for all functions with four or fewer variables is given and a comprehensive synthesis method is provided. For the 21 Microelectronics Center of North Carolina (MCNC) benchmarks presented in this paper, the proposed approach yields an average reduction of 9.6% in the number of gate counts and 7.6% in the number of levels when compared with the best existing method.

FPGA interconnect modeling for lifetime failure detection

As FPGAs move into nanometer regime CMOS technology, new performance and lifetime limitations have started showing up. The process variation effects cause undesired behavior of the circuit as transistor dimensions decrease. This work makes an effort to understand the importance of routing in FPGAs and its impact on the performance of nanometer scale FPGAs. Lifetime failure of FPGAs can be detected by observing the variation in the delay performance from newly developed or developing faults. In this paper, we develop models of interconnect and switching networks that enhance delay estimation. Circuit simulations performed using these models are compared with the timing simulation results from Xilinx development tools.