Mohammed Shafiqul Hai

A Scalable Space–Time Multi-plane Optical Interconnection Network Using Energy-Efficient Enabling Technologies [Invited]

This paper presents an energy-efficient multi-plane optical interconnection network to interconnect servers in a data center. The novel architecture uses the time domain to individually address each port within a card and the space domain to address each card. Optical enabling technologies passively time-compress serial packets by exploiting the wavelength domain and perform a broadcast-and-select to a destination card with minimum power dissipation. Scalability of both the physical layer and the overall power dissipation of the architecture is shown to be enhanced with respect to the existing interconnection network architectures based on space and wavelength domains. The space-time network architecture is scalable up to 216 ports with space-switches exhibiting energy efficiency of the order of picojoules per bit, thanks to the self-enabled semiconductor-optical-amplifier-based space-switches.

A 16 GHz silicon-based monolithic balanced photodetector with on-chip capacitors for 25 Gbaud front-end receivers

In this paper, a Germanium-on-Silicon balanced photodetector (BPD) with integrated biasing capacitors is demonstrated for highly compact monolithic 100 Gb/s coherent receivers or 25 Gbaud front-end receivers for differential or quadrature phase shift keying. The balanced photodetector has a bandwidth of approximately 16.2 GHz at a reverse bias of -4.5 V. The balanced photodetector exhibits a common mode rejection ratio (CMRR) of 30 dB. For balanced detection of return-to-zero (RZ) differential phase shift keying (DPSK) signal, the photodetector has a sensitivity of -6.95 dBm at the BER of 10(-12). For non-return-to-zero (NRZ) on off keying (OOK) signal, the measured BER is 1.0 × 10(-12) for a received power of -1.65 dBm at 25 Gb/s and 9.9 × 10(-5) for -0.34 dBm at 30 Gb/s. The total footprint area of the monolithic front-end receiver is less than 1 mm(2). The BPD is packaged onto a ceramic substrate with two DC and one RF connectors exhibits a bandwidth of 15.9 GHz.

Multichannel Transmission Through a Gold Strip Plasmonic Waveguide Embedded in Cytop

In this paper, we experimentally characterize a low-loss polymer-based plasmonic waveguide and present its system-level performance for transmitting multiple on-off keying modulated channels (4 × 49 Gb/s). The same waveguide also exhibits the capability of transmitting multiple differential phase shift keying modulated channels (4 × 10 Gb/s). Signal transmission has been verified through bit-error-rate measurements. The plasmonic waveguide consists of a 3.6-mm-long, 5-μm-wide, and 35-nm-thick gold strip embedded in Cytop polymer and exhibits a total optical insertion loss of approximately 13 dB at a free-space optical wavelength of 1.55 μm.

Design of a 50-Gb/s SOI-Based DPSK Demodulator for Dense Photonic Integration

A silicon-on-insulator (SOI)-based Mach-Zehnder delay interferometer fabricated in a 220-nm height and 500-nm width SOI strip waveguide technology is presented. The delay line length of 20 ps in the interferometer is optimized to a data rate of 50 Gb/s. The measured insertion loss of the device is 16 dB, including the facet losses. At the output of the demodulator, an approximately 20-dB extinction ratio is achieved. Low bit error rate (BER) measurement (10-9) is reached for a demodulated signal with an optical-signal-to-noise ratio of 15.8 dB at the photodetector. Error-free performance (BER<; 10-9) of the SOI-based DPSK demodulator is experimentally demonstrated at 50 Gb/s.

A Ring-Based 25 Gb/s DAC-Less PAM-4 Modulator

A novel PAM-4 12.5 Gbaud/s inter-coupling modulator based on a Mach-Zehnder interferometer assisted ring resonator is demonstrated. The 25 Gb/s PAM-4 optical signal is generated by driving the modulator with two independent electrical signals with an amplitude of 3 Vpp at 2 V reverse bias. Reverse bias operation mode of the modulator enables achieving an electro-optic (EO) bandwidth of approximately 14 GHz without preemphasis of the electrical driving signals or equalization techniques. This configuration successfully simplifies the operation of the modulator in generating PAM-4 signals without the need for a digital-to-analog converter (DAC). Experimental results show proper generation of a PRBS data stream. The proposed modulator has a compact footprint of 0.48 mm2 with a bandwidth density of 52.08 Gb/s/mm2.

Simultaneous high-capacity optical and microwave data transmission over metal waveguides

The implementation of power efficient and high throughput chip-to-chip interconnects is necessary to keep pace with the bandwidth demands in high-performance computing platforms. In recent years, considerable effort has been made to optimize inter-chip communications using traditional copper waveguides. Also, optical links are extensively investigated as an alternative technology for fast and efficient data routing. For the first time, we experimentally demonstrate simultaneous microwave and optical high-speed data transmission over metallic waveguides embedded in polymer. The demonstration is significant as it merges two layers of communications onto the same structure towards increased aggregated bandwidth, and energy-efficient data movement.

A Silicon Photonic Integrated Packaged Coherent Receiver Front-End For Soft-Decision Decoding

In this paper, a packaged integrated coherent receiver and optical front-end for soft decision based on 25 Gbaud/s quadrature phase-shift keying (QPSK) is investigated for on-chip applications. The front-end consists of a 90° hybrid, balanced photodetectors, and unbalanced couplers monolithically integrated in a CMOS compatible silicon-on-insulator technology. The silicon photonic device is packaged onto a ceramic substrate with RF and dc connectors. The proposed front-end is an example of integration of system on chip. The integrated solution is able to provide 6.2 dB performance improvements over uncoded system without error correction. The front-end outperforms optical system with hard-decision forward error correction by 2.2 dB at the BER of 10-7.

Thermally stable 50 Gb/s SOI DPSK demodulator

A fabricated 50 Gb/s silicon-on-insulator (SOI) Mach-Zehnder demodulator exhibits over 90 % improvement in thermal stability with 0.05 nm/°C of its spectral profile compared to 0.9 nm/°C for a non-compensated demodulators.

Automated characterization of SiP MZI-based switches

A testing methodology for commercial automated test equipment (ATE) conventionally used for electrical integrated circuits is developed for photonic integrated circuits. The method is assessing by efficiently characterizing a packaged low-port optical switch matrix.

A monolithic optical front-end for soft-decision error correction decoders

We investigate a monolithic optical front-end for soft-decision low-density parity-check (LDPC) decoders based on 100 Gb/s polarization division multiplexed quadrature shift keying (PM-QPSK) coherent detection.