Odile Liboiron-Ladouceur

A fully implemented 12 /spl times/ 12 data vortex optical packet switching interconnection network

A fully functional optical packet switching (OPS) interconnection network based on the data vortex architecture is presented. The photonic switching fabric uniquely capitalizes on the enormous bandwidth advantage of wavelength division multiplexing (WDM) wavelength parallelism while delivering minimal packet transit latency. Utilizing semiconductor optical amplifier (SOA)-based switching nodes and conventional fiber-optic technology, the 12-port system exhibits a capacity of nearly 1 Tb/s. Optical packets containing an eight-wavelength WDM payload with 10 Gb/s per wavelength are routed successfully to all 12 ports while maintaining a bit error rate (BER) of 10/sup -12/ or better. Median port-to-port latencies of 110 ns are achieved with a distributed deflection routing network that resolves packet contention on-the-fly without the use of optical buffers and maintains the entire payload path in the optical domain.

The Data Vortex Optical Packet Switched Interconnection Network

A complete review of the data vortex optical packet switched (OPS) interconnection network architecture is presented. The distributed multistage network topology is based on a banyan structure and incorporates a deflection routing scheme ideally suited for implementation with optical components. An implemented 12-port system prototype employs broadband semiconductor optical amplifier switching nodes and is capable of successfully routing multichannel wavelength-division multiplexing packets while maintaining practically error-free signal integrity (BER < 10-12) with median latencies of 110 ns. Packet contentions are resolved without the use of optical buffers via a distributed deflection routing control scheme. The entire payload path in the optical domain exhibits a capacity of nearly 1 Tb/s. Further experimental measurements investigate the OPS interconnection networks flexibility and robustness in terms of optical power dynamic range and network timing. Subsequent experimental investigations support the physical layer scalability of the implemented architecture and serve to substantiate the merits of the data vortex OPS network architectural paradigm. Finally, modified design considerations that aim to increase the network throughput and device-level performance are presented.

Energy-Efficient Design of a Scalable Optical Multiplane Interconnection Architecture

As the power dissipation of data centers challenges their scalability, architectures for interconnecting computers, or servers must simultaneously achieve high throughput at peak utilization and power consumption proportional to utilization levels. To achieve this goal, this paper proposes the use of an optical multiplane interconnection network, named space-wavelength (SW) switched architecture, able to route and switch packets between servers (on cards) and between processors within a card (or card ports). SW architecture exploits the space domain to address the destination card and the wavelength domain to address the destination port on a per-packet basis. Scalability and energy efficiency of the considered architecture are quantified and compared to typical single-plane architectures. Not only can the SW multiplane architecture achieve higher throughput by exploiting two switching domains, but its performance is shown to be highly scalable with network utilization. More importantly, higher performance is reached with an energy efficiency superior to single-plane architectures. The excellent energy efficiency is achieved using optical devices with low idle power.

Physical Layer scalability of WDM optical packet interconnection networks

The physical layer scalability of a packet-switched optical interconnection network utilizing semiconductor optical amplifier (SOA) switch elements is investigated experimentally and with numerical modeling. Optical packets containing payloads of multiple wavelength-division-multiplexing (WDM) channels are propagated through cascaded SOA-based switching nodes in a recirculating test-bed environment. Experiments show that bit-error rates (BERs) below 10/sup -9/ can be maintained through 58 switching nodes for the entire eight-channel 10-Gb/s-per-channel payload distributed over 24.2 nm of the C-band. When the packet payload consists of a single 10-Gb/s channel, 98 node hops can be traversed before a BER of 10/sup -9/ is exceeded. In conjunction with the experiments, a novel phenomenological modeling technique is developed in order to forecast the scalability of SOA-based WDM packet interconnection networks. This technique is shown to yield results that correlate well with the experimental data. These investigations are presented as predictors of the physical limitations of large-scale WDM packet-switched networks.

160-Gb/s, 16-Channel Full-Duplex, Single-Chip CMOS Optical Transceiver

We report a single-chip CMOS optical transceiver incorporating sixteen 10-Gb/s transmitter and receiver channels for a 160 Gb/s aggregate bit rate. The transceiver consumes 15.6 mW/Gb/s with an area efficiency of 9.4 Gb/s/mm2 per link.

A Scalable Space–Time Multi-plane Optical Interconnection Network Using Energy-Efficient Enabling Technologies [Invited]

This paper presents an energy-efficient multi-plane optical interconnection network to interconnect servers in a data center. The novel architecture uses the time domain to individually address each port within a card and the space domain to address each card. Optical enabling technologies passively time-compress serial packets by exploiting the wavelength domain and perform a broadcast-and-select to a destination card with minimum power dissipation. Scalability of both the physical layer and the overall power dissipation of the architecture is shown to be enhanced with respect to the existing interconnection network architectures based on space and wavelength domains. The space-time network architecture is scalable up to 216 ports with space-switches exhibiting energy efficiency of the order of picojoules per bit, thanks to the self-enabled semiconductor-optical-amplifier-based space-switches.

Demonstration of a complete 12-port Terabit capacity optical packet switching fabric

We report on the implementation of a complete 12-port Data Vortex optical packet switching fabric containing 36 fully-interconnected nodes. Correct routing behavior is verified for 14-channel WDM packets, and latencies below 60 ns are achieved.

Designing Energy-Efficient Data Center Networks Using Space-Time Optical Interconnection Architectures

This paper considers a space-time interconnection architecture (STIA) based on optical devices and proposes its introduction in data center networks. The power consumption of the STIA is modeled, accounting for the energy proportionality of the optical devices in the STIA. Using such a model, a STIA-based network is designed using three different topologies, tree, folded Clos, and flattened butterfly, and optimized for power efficiency. Results show that, for a fixed topology, small-size STIAs are an energy-efficient solution for data center networks and allow a power reduction of more than an order of magnitude with respect to the Ethernet-based network. The comparison for the same bisection bandwidth shows that folded Clos and flattened butterfly outperform tree, whose power consumption is strongly dependent on the oversubscription ratio selected.

Bit-parallel message exchange and data recovery in optical packet switched interconnection networks

Multiwavelength optical messages encoded in a bit-parallel fashion are successfully routed through five switching nodes of a 12-port optical packet switching interconnection network. The data payloads are entirely recovered and processed at the destination node using an embedded clock signal with a measured clock-to-data skew tolerance window of 150 ps.

Application and demonstration of a digital test core: optoelectronic test bed and wafer-level prober

Abstract A multi-purpose digital test core utilizing programmable logic has been introduced [1,2] to implement many of the functions of traditional automated test equipment (ATE). While previous papers have described the theory, this paper quantifies the results and presents additional applications with improved methods operating up to 4.4Gpbs. The digital test core provides a substantial number of programmable I/O for testing circuits and systems. It may be used either to enhance the capabilities of ATE or to provide autonomous testing within large systems or arrays of components. This technique has been expanded upon to produce greater functionality at higher frequencies. Based upon limitations of current ATE and BIST, the need for the digital test core is described. The test core concept is reviewed within an opto-electronic pattern generator and sampler with an eventual goal of terabit-per-second aggregate data rate. The performance of the device is discussed, and a second application of the digital test core is introduced as a nano-scale wafer-level embedded tester.