Mohan Nagar

Electrical performance assessment of advanced substrate technologies for high speed networking applications

High end computing and networking applications continue to drive silicon technologies for higher performance, increased bandwidth and frequency. The drive for higher performance has resulted in increased power dissipation. A method for mitigating power dissipation includes reducing the voltage but unfortunately the consequence is reduced noise margin. This paper evaluates the electrical performance and assess the design trade-offs of two new advanced packaging concepts designed to improve the PDN (Power Delivery Network) in a typical ASIC (Application Specific Integrated Circuit) by introducing features for enhancing core power decoupling and decreasing inductance and impedance in the organic substrate.

Assembly and reliability of advanced packaging technologies in high speed networking applications

High end networking and computing applications continue to drive silicon technologies for higher data rates and increased bandwidth. The push for silicon performance with 45nm and 32nm devices also drives a need for packaging performance to deliver clean and efficient power to the device. This paper compares the electrical performance, assembly and reliability of various advanced packaging technologies, which are aimed to improve the DC and AC power delivery network (PDN) in a network ASIC (Application Specific Integrated Circuit). A baseline ASIC component was redesigned and fabricated into (1) a hybrid package placing the baseline ASIC onto a customized interposer board fabricated with both conventional and advanced high-capacitance laminate systems (2) a package utilizing a conventional substrate having capacitors interspersed between the BGA-balls, (3) a package utilizing an organic substrate with an embedded bulk array capacitor, and (4) a package using a coreless substrate. The bare substrates and ASIC component were assembled through conventional high volume processes whenever possible. The ASIC components were then assembled onto line cards using conventional board level assembly parameters and techniques. Electrical and reliability testing were performed at both device level and product level. For electrical measurement, improvements to the PDN were quantified by measuring the power rail noise and clock jitter and comparing each package variant to the performance of the baseline ASIC. The package design, signal routing, device, and system, assembly and test environments are essentially unchanged; the differences are attributed primarily to the substrate and package technology itself. A strong correlation between simulation results and electrical performance data was observed. A qualitative/quantitative system of comparing the cost, complexity and capability of each solution was used to evaluate their viability for implementation into high volume manufacturing. Package and Board Level Reliability (BLR) was conducted on the most viable solutions.

Effect of thermal interface materials on manufacturing and reliability of Flip Chip PBGA and SiP packages

Power and power density increase in microelectronics is a major challenge for packaging high performance ASIC and microprocessor devices. The thermal interface material (TIM) used between the chip and the heat spreader of the Flip Chip Plastic Ball Grid Array (FC-PBGA) package plays a very important role in the package thermal performance. Not only does it affect package thermal performance, it can also affect assembly yield and package reliability during manufacturing and normal operation. In this study attention has been focused on improving thermal performance, manufacturing yield and reliability of the flip-chip PBGA single chip packages and the System in Package (SiP) modules. Computational Fluid Dynamics (CFD) software was used to investigate the effect of TIM on FC-PBGA thermal performance. The effect of thermal interface material was then studied for controlling the interaction between the heat spreader and the FC-PBGA SiP module to reduce module warpage and to improve module assembly yield. Qualification of TIM for FC-PBGA at both the component level and the system level was discussed. Component level testing data showed that the thermal characteristics and mechanical integrity of the TIM selected can be evaluated by using the same stress conditions used in package reliability qualification. Finally, system level non- operational humidity test results showed that good mechanical reliability at the thermal interface of the FC-PBGA can be achieved by optimizing the heat spreader attaching process.

Impact of system level thermal solution on the interconnect reliability of high performance and high heat dissipating CSP package

A custom SRAM was developed for high performance and high reliability network switching applications using 90 nm low-k silicon technology. It is a 13.6 mm x 18.4 mm flip chip chip scale package (CSP) with a 11.12 mm x 16.36 mm die. The package has 838 BGA balls at 0.5 mm pitch. The 0.5 mm ball pitch CSP minimizes electrical package parasitics and enables higher data rate performance. However, the high aspect ratio of the die-to-package area leaves very little room for underfill dispensing and no room for a stiffener ring attachment. In addition, the high heat dissipation of the device requires the use of a metal heatspreader flip chip package as opposed to an overmolded flip chip package solution. The package design coupled with a large die and high I/O count presents significant challenges in the package assembly process and interconnect reliability. A lower glass transition (Tg) underfill material is typically preferred to reduce package warpage and to reduce the stress in the low-k dielectric caused by CTE mismatch between the silicon die and package materials. However, for high power applications where the operating temperature is very close to the underfill Tg, the system level thermal solution must be optimized for improved cooling while at the same time ensuring that the interconnect and package reliability at the system application level is not compromised. In this paper, both Experimental and Finite Element analyses were performed to investigate the key system level thermal solution design parameters that impact package interconnect reliability. The effect of heatsink compressive loading on the thermal excursions, the underfill material, and the interconnect metallurgy was evaluated. In addition to the compressive loading effect, the effect of the heatsink attachment method on interconnect reliability was also investigated. Three dimensional fatigue analyses were performed to derive the hysteresis loops for different test cases, to understand the interaction between the heatsink attachment method and the package material and design variables. The finite element model data was benchmarked against experimental data to determine the optimal design conditions for effective thermal cooling without compromising interconnect reliability. Real time pressure measurement and failure analysis were also performed to understand the potential failure modes and failure rates occurring in the system level design. Finally, recommendations are provided on ways to mitigate critical failure modes in the thermal and interconnect design of such complex flip chip CSP packages at the system level.

Ultra large System-in-Package (SiP) module and novel packaging solution for networking applications

With increasing data traffic requirements to support mobile devices, tablets and computers, the need for faster internet traffic is mushrooming. The routers and switches used to drive network traffic need to deliver high bandwidth and speed. Key to achieving this high speed and bandwidth is ensuring closer integration between the Application Specific Processors (ASICs) and Memory devices. Consequently, it is important to place memories as close as possible to ASICs. Standard Printed Circuit Board (PCB) design rules make it difficult to place several memories very close to ASICs, and PCBs are already densely populated. Consequently, there are two prevailing technologies that are used to increase density: Through Silicon Vias (TSVs) or System-in-Package (SiP) modules. TSVs are still in early stages of development, whereas smaller SiP modules have already been used in Networking [1, 2]. In this study, we outline an innovative SiP module solution: Implementation of a very large (90 × 90 mm) SiP module with 14 packaged DDR3 memories and 1 large flip low K chip ASIC mounted on a common Ball Grid Array (BGA) substrate. This is likely the largest organic BGA module ever built. Finite Element Analysis was performed to estimate the optimal stiffener and lid parameters for minimal warpage. Complete substrates were assembled with key metrics measured at each step of the assembly process. Excellent coplanarity was achieved in the assembly process. The SiP modules were then mounted on PCBs and the board level assembly process characterized. The modules were successfully mounted on the PCBs. The procedures and key learnings from this evaluation will be outlined in this study.

Mixed Pitch BGA (mpBGA) packaging development for high bandwidth-high speed networking devices

High speed network packaging solutions have pushed the limits of known manufacturing technology into previously untested realms. Next generation ASICs and SiP/MCMs are requiring packages in excess of 60mm × 60mm. These large package sizes present both significant manufacturability and reliability challenges. Developing new solutions which can adequately accommodate the needs of high speed interconnect while concurrently mitigating package size growth and the consequential reliability and manufacturability risks which result, is essential for maintaining a supply equilibrium at a sustainable cost. This paper discusses the manufacturing process and the component reliability of a large body size (55×55mm) ASIC package TV using 40nm ELK Si technology and a Mixed Pitch Ball Grid Array (mpBGA) with BGA-side capacitance on both thin core (0.4mm) and 8+1 coreless substrates. Suitable for use at any body size, mpBGA combines tighter BGA pitch (0.94mm) and the option for BGA-side capacitance to enable optimal package decoupling and increased interconnect density. mpBGA provides a means for mitigating package size growth by inherently extending the usefulness of smaller package sizes, thereby minimizing both the package reliability risks as well as the cost associated with proving in the “next” body size up (i.e increasing from 55×55mm to 60×60mm packages). The preferred method for assembly and design of mpBGA packages on both coreless and thin core substrates will be discussed including: (1) assembly process capability, (2) preferred board level design stack-up and (3) preferred package design footprint incorporating the BGA-side capacitors. A preferred BOM has been identified for the thin-core 55×55mm package which has resulted in full-pass of all relevant L1 reliability tests (MSL-4 preconditioning, HTS, uHAST and 1000TCB). Additionally, it is shown that the package co-planarity of the 55×55mm thin-core test vehicle is within the required 8 mil maximum for large body size flip chip BGA packages.

Reliability Challenges in 2.5D and 3D IC Integration

Today, applications like data center/cloud, mobility and Internet of Things (IoT) are key market drivers for semiconductor industry. To meet the requirements of next generation Information and Communication Technology (ICT) systems, the packaging technology has to evolve along with the Integrated Circuit (IC) technology scaling. At the same time, design and development of packages have to meet the cost, performance, form factor and reliability goals. In this paper, we will examine new advances in packaging technology to maintain the IC scaling edge, as well as the role of new emerging 2.5-dimensional (2.5D) and 3-dimensional (3D) IC packaging platforms for addressing the gap seen between the slowdown of Moores Law scaling and the ever-increasing system integration requirements. We will then review the new elements introduced by 2.5D and 3D IC integration and the potential risks to reliability of the final products. A detailed review on technology and component level qualification will be presented. It will then be followed by three case studies on board level reliability validation. One case is about evaluating a Dual In-line Memory Module (DIMM) with 3DS DDR3 for server applications. The second case is on a 3D IC package with 5 dice stacked and interconnected with Through-Silicon-Vias (TSV). And the third package is a 3D System-in-Package with multiple 3D die-stacks packaged with an organic interposer. The results from reliability testing are used to understand the driving forces and failure mechanism acceleration and to define the application space of the 3D IC packages for networking applications.

Large scale System-in-Package (SiP) module for future networking products

With increasing data traffic requirements to support mobile devices, tablets and computers, the need for faster internet traffic is mushrooming. The routers and switches used to drive network traffic need to deliver high bandwidth and speed.