Weidong Xie

Pb-free solder joint reliability of fine pitch chip-scale packages

Chip-scale package (CSP) is commonly seen on high density boards as it minimizes the foot print while packed more functionality into one component. Board level reliability concern over CSPs is that finer pitch limits the solder ball size attached and the stencil thickness used in assembly which leads to much smaller joint volume and standoff while larger die-to-package ratio typically means higher stress level caused by the CTE mismatch. Prior studies have shown that the grain orientation may impact SnAgCu solder joint reliability. With less solder volume, the joint reliability of fine pitch SnAgCu solder may be more sensitive to the grain size, grain orientation, and IMC formation within the bulk solder. The purpose of the study is to evaluate the board level reliability of Pb-free ball grid array (BGA) packages with ball pitch smaller than 0.5mm under different packaging and assembly conditions. Based on a test vehicle with 0.4mm pitch daisy-chained CVBGA, the impact on solder joint reliability from a wide spectrum of variables such as PCB thickness, SMT configuration, die size, package pad finish, and mini cycle profiling has been investigated. The results of this study enable us to better understand the Pb-free fine pitch joint behaviors under different conditions and the factors that have significant impact on joint reliability. Isothermal aging effect has also been studied, will be presented in a separated paper, which demonstrated that isothermal aging could significantly degrade joint reliability for fine pitch packages. The ATC results proved that the fine pitch packages may underperform the components with regular 0.8–1.0mm pitch therefore extra attention needs to be paid on fine pitch components while converting high reliability products to Pb-free.

Parametric acceleration transforms for lead-free solder joint reliability under thermal cycling conditions

The conversion to Pb-free solders has already been implemented in the consumer market. However, the transition to Pb-free solders in the high performance, mission critical networking/server industry has not yet been fully implemented.

Effect of Board Thickness on Sn-Ag-Cu Joint Interconnect Mechanical Shock Performance

The mechanical stability of solder joints with Sn-Ag-Cu alloy joints on various board thicknesses was investigated with a high G level shock environment. A test vehicle with three different board thicknesses was used for board drop shock performance tests. These vehicles have three different strain and shock level condition couples per board, and are used to identify the joint stability and failure modes based on the board responses. The results revealed that joint stability is sensitive to board thickness. The board drop shock test showed that the first failure location shifts from the corner location near the standoff to the center with increased board thickness due to the shock wave response. From analysis of the thickness variation and failure cycle number, the strain rate during the pulse strain cycle is the dominant factor, which defines the life cycle number per board thickness, and not the maximum strain value. The failure location shift and the shock performance differentiation are discussed from the perspective of maximum principal strain, cycle frequency and strain rate per cycle.

The impact of microstructure evolution, localized recrystallization and board thickness on Sn-Ag-Cu interconnect board level shock performance

The mechanical stability of solder joints with SnAgCu alloy on various board thicknesses were investigated in a high G level shock environment. A test vehicle with 31mil, 62mil and 93mil board thickness, which has three different strain and shock level condition combination per board, was used to identify the joint stability and failure modes. The results revealed that joint stability is sensitive to board thickness and that the first failure location shift from the corner location near the stand off to the center with increased board thickness. Also the impact of isothermal aging and fine grain structure transformation on mechanical shock performance of solder joints were investigated. The results revealed that joint stability during shock loading is sensitive to the level of shock that can be absorbed during each shock cycle based on the capability of single to multi grain transformation. The localized fine grain structure distributions were analyzed to identify correlations between the microstructure evolution and shock performance.

Ultra large System-in-Package (SiP) module and novel packaging solution for networking applications

With increasing data traffic requirements to support mobile devices, tablets and computers, the need for faster internet traffic is mushrooming. The routers and switches used to drive network traffic need to deliver high bandwidth and speed. Key to achieving this high speed and bandwidth is ensuring closer integration between the Application Specific Processors (ASICs) and Memory devices. Consequently, it is important to place memories as close as possible to ASICs. Standard Printed Circuit Board (PCB) design rules make it difficult to place several memories very close to ASICs, and PCBs are already densely populated. Consequently, there are two prevailing technologies that are used to increase density: Through Silicon Vias (TSVs) or System-in-Package (SiP) modules. TSVs are still in early stages of development, whereas smaller SiP modules have already been used in Networking [1, 2]. In this study, we outline an innovative SiP module solution: Implementation of a very large (90 × 90 mm) SiP module with 14 packaged DDR3 memories and 1 large flip low K chip ASIC mounted on a common Ball Grid Array (BGA) substrate. This is likely the largest organic BGA module ever built. Finite Element Analysis was performed to estimate the optimal stiffener and lid parameters for minimal warpage. Complete substrates were assembled with key metrics measured at each step of the assembly process. Excellent coplanarity was achieved in the assembly process. The SiP modules were then mounted on PCBs and the board level assembly process characterized. The modules were successfully mounted on the PCBs. The procedures and key learnings from this evaluation will be outlined in this study.

Experimentally validated analysis and parametric optimization of monotonic 4-point bend testing of advanced BGA packages

With continuing miniaturization and more prevalent use of Ball Grid Array (BGA) packages in the microelectronics industry, the mechanical strength of Printed Circuit Board Assemblies (PCBAs) with BGA packages is becoming very critical. In a variety of applications ranging from smart phones to high end switches and routers, the mechanical robustness of PCBAs is becoming the key differentiator in product reliability. To enable a standard way to benchmark mechanical reliability, the IPC/JEDEC-9702 test method was developed several years ago. The test method has helped compare different PCBAs to optimize overall mechanical reliability. However, a key challenge with mechanical testing is that by the time the testing is performed, it is too time consuming and expensive to make changes to the package if its mechanical reliability needs improvement. In this study, bending tests for various BGA packages have been conducted based on the IPC/JEDEC-9702 standard, under different applied deflections to obtain the required data for studying the failure modes. Three-dimensional Finite Element Models (FEM) were developed to understand the relationship between PCB strain and solder joint strain. The strain values at different locations in the PCBA were estimated from the model, and compared with experimental data. Good agreement between model predictions and experimental data has been obtained. Then, a series of FEM analyses were performed with different design parameters. High performance cluster computing was used to reduce computation time without compromising accuracy. Finally, based on the results presented in this study, optimization analysis was performed to improve BGA mechanical reliability for any given geometry.

Validated methodology for short-design-cycle chip, package and system interaction

While in the past, the silicon, package and system could be designed sequentially, at silicon nodes less than 40nm, the interconnects between the chip, package and system are becoming the limiting factor in performance and reliability. Hardware designers need to know upfront, what tradeoffs they need to make, to design an optimal system level solution. Quantitative estimates on the optimal package materials, assembly processes and design rules are required upfront as opposed to much later in the design process: In the past, several iterations of learning cycle test vehicles and modeling were used to address some of these questions, but with design cycles shrinking to less than a year in some cases, there is no time for repeated learning cycles and qualitative numerical models that only give general trends. Consequently, the industry needs a methodology that can give optimal Chip Package System Interaction (CPSI) design parameter ranges and reduce the number of prototype iterations. A key requirement in CPSI is the ability to accurately scale from chip level interconnects (on the order of a few microns), to system level features (on the order of several millimeters). Historically, CPSI has been evaluated using conventional finite element models in which smeared or submodeling techniques were used to approximate the mechanics of the assembly. Such approximations were necessary to achieve manageable computation times. However, these approximations have relegated the numerical models to qualitative trend assessments as opposed to a more regimented quantitative analysis. In this paper, a complete methodology is presented, that can more accurately capture the mechanics of CPSI without requiring unreasonable computation time for multiple design iterations. The methodology is a combination of experimental evaluation and numerical analysis. Both used iteratively achieve the intended purpose: reduce overall design time with less cost and design iterations giving quantitative estimates. Each process step, starting from chip attach and ending with ball attach and board level assembly, was experimentally characterized for the 40nm silicon node Bill of Materials (BOM) and compared against numerical models. The iterative experimental correlation and the resulting model methodology are outlined in detail in this paper. Having experimentally validated the methodology, the effects of chip thickness, substrate thickness, bump design, underfill material, lid, stiffener and lid attachment on package warpage were determined and compared with experimental data. The corresponding impact of these factors on bump fatigue life and die level stresses was also determined. The relationship between board level assembly parameters and package and chip design variables was also determined. Finally, next generation on-demand cloud computing resources were used to further reduce computation times without sacrificing accuracy. A parametric study of the computing resources and processing times was also performed to help designers select the best computing resources for optimal design for faster times to market and product reliability.

Mixed Pitch BGA (mpBGA) packaging development for high bandwidth-high speed networking devices

High speed network packaging solutions have pushed the limits of known manufacturing technology into previously untested realms. Next generation ASICs and SiP/MCMs are requiring packages in excess of 60mm × 60mm. These large package sizes present both significant manufacturability and reliability challenges. Developing new solutions which can adequately accommodate the needs of high speed interconnect while concurrently mitigating package size growth and the consequential reliability and manufacturability risks which result, is essential for maintaining a supply equilibrium at a sustainable cost. This paper discusses the manufacturing process and the component reliability of a large body size (55×55mm) ASIC package TV using 40nm ELK Si technology and a Mixed Pitch Ball Grid Array (mpBGA) with BGA-side capacitance on both thin core (0.4mm) and 8+1 coreless substrates. Suitable for use at any body size, mpBGA combines tighter BGA pitch (0.94mm) and the option for BGA-side capacitance to enable optimal package decoupling and increased interconnect density. mpBGA provides a means for mitigating package size growth by inherently extending the usefulness of smaller package sizes, thereby minimizing both the package reliability risks as well as the cost associated with proving in the “next” body size up (i.e increasing from 55×55mm to 60×60mm packages). The preferred method for assembly and design of mpBGA packages on both coreless and thin core substrates will be discussed including: (1) assembly process capability, (2) preferred board level design stack-up and (3) preferred package design footprint incorporating the BGA-side capacitors. A preferred BOM has been identified for the thin-core 55×55mm package which has resulted in full-pass of all relevant L1 reliability tests (MSL-4 preconditioning, HTS, uHAST and 1000TCB). Additionally, it is shown that the package co-planarity of the 55×55mm thin-core test vehicle is within the required 8 mil maximum for large body size flip chip BGA packages.

Effect of Local Grain Distribution and Enhancement on Edgebond Applied Wafer-Level Chip-Scale Package (WLCSP) Thermal Cycling Performance

The demand on reliable Wafer level chip scale packages (WLCSP) are getting higher due to the need of small form factor and cost. As demonstrated in earlier publications the degradation and deformation mechanism show microstructure evolution associated with the thermal cycling induced damage accumulation. The mechanism, leading to crack initiation and propagation during thermal cycling by sub-grain boundary development can be observed as a general damage accumulation mechanism in various solder joints. The correlation between crack propagation and localized recrystallization are compared in a series of cross section analyses on thermal cycled WLCSP components with normal and elevated temperature thermal cycling conditions. Damage accumulated solder joint locations are identified and an attempt of using edge-bond materials to strengthen the localized solder joints demonstrate that the Tg and CTE needs adjustment to have the thermal cycling performance enhancement. Edge-bond material applied components show either a shift of damage accumulation to a more localized region, thus potentially accelerated the degradation, or mitigate the distribution resulting in an enhancement of thermal cycling based on their Tg and CTE properties. The edge-bond applied WLCSPs were thermally cycled from 0oC to 100oC with 10min. dwell time, and to simulate the function temperature environment, components were also tested at elevated temperature cycles for comparison. Using an analysis on localized distribution of recrystallized areas inside the solder joint provide more information on the localized microstructure evolution during thermal cycling. The results show that the crack propagation distribution and recrystallization region correlation can explain the enhancement and potential degradation mechanisms and support the damage accumulation history in a more efficient way.

Experimentally validated analysis and parametric optimization of mechanical shock testing of advanced BGA packages

With continuing miniaturization and more prevalent use of Ball Grid Array (BGA) packages in the microelectronics industry, the mechanical strength of Printed Circuit Board Assemblies (PCBAs) with BGA packages is becoming very critical. In a variety of applications ranging from smart phones to high end switches and routers, the mechanical robustness of PCBAs is becoming the key differentiator in product reliability. IPC/JEDEC-9704 test method was developed several years ago to enable a standard way to benchmark mechanical reliability. The test method has helped compare different PCBAs to optimize overall mechanical reliability. However, a key challenge with mechanical shock testing is that by the time the testing is performed, it is too time consuming and expensive to make changes to the package if its mechanical reliability needs improvement. In this study, shock tests for various BGA packages have been conducted based on the IPC/JEDEC-9704 standard, under different applied G values to obtain the required data for studying the failure modes. Three-dimensional Finite Element Models (FEM) were developed to understand the relationship between PCB strain and corner solder joint strain. The strain values on the PCB close to the package were estimated from the model and compared with experimental data. A series of FEM analyses were performed with different design parameters. Finally, based on the results presented in this study, optimization analysis was performed to improve BGA mechanical reliability for any given geometry.