Mohd Nazri Mohd Warip

Energy consumption optimization with Ichi Taguchi method for Wireless Sensor Networks

Wireless Sensor Networks (WSN) consists of sensor nodes for monitoring and reporting sensible changes on a field to a specific server. One of the applications of WSN is large area monitoring, where sensor nodes are placed in far fields with limited power sources. Due to the adhered reason, the energy consumption of sensor nodes is considered as one of the major challenge in WSN. Many factor in WSN contributes to energy consumption such as Medium Access Control protocol (MAC), the network topology, and routing protocol. With the variety of factors that affects the energy consumption in WSN; the challenge of optimizing WSN networks toward a low energy consumption is becoming a hard problem. In the literature many efforts are paid for designing, implementing, and improving protocols in terms of power consumption. However, few efforts are paid for optimizing the existing protocols and other network parameters toward a green technology. This paper focuses in WSN infrastructure and protocols optimization by introducing the Ichi Taguchi (Taguchi) optimization method. Taguchi method is used to predict the best design parameters to achieve optimal performance parameters. Moreover, Taguchi method is used to optimize the energy consumed by sensor nodes against network protocols and network topology design parameters. A simulation experiments are curried out on the discrete event simulator OMNET++ for the purposes of this research paper. The obtained results show the impact of the network protocols toward the energy consumption. Furthermore, a proposed network topology and protocols set is introduced, and compared against the existing once.

Energy-Efficient Remote Healthcare Monitoring Using IoT: A Review of Trends and Challenges

The emergence of Internet and technologies such as Wireless Sensor Network (WSN) has created another platform of Wireless Body Area Network (WBAN) and also an ever growing new area of Internet of Thing (IoT). A WBAN offers a flexibility and mobility to health monitoring system. Most of WBAN is made up of several small and light-weighted battery-operated sensor nodes and lead to energy-constrained system. Thus, an energy-efficient WBAN system is crucially needed to make the network last longer. In addition, data reliability and data transmission is important to make the system more effective. IoT concept helps in forming an interaction of things in the surrounding as well as support data storage (database) for collected vital body sign by the sensors. In this paper, we review the concept and design of energy-efficient WBAN and contribution of IoT in healthcare monitoring system.

Hardware Implementation of MFCC-Based Feature Extraction for Speaker Recognition

The most important issues in the field of speech recognition and representative of the speech is a feature extraction. Feature extraction based Mel Frequency Cepstral Coefficient (MFCC) is one the most important features required among various kinds of speech application. In this paper, FPGA-based for speech features extraction MFCC algorithm is proposed. The complexities of computational as well as the requirement of memory usage are characterized, analyzed, and improved. Look-up table (LUT) scheme is used to deal with the elementary function value in the MFCC algorithm and fixed-point arithmetic is implemented to reduce the cost under accuracy study. The final feature extraction design is implemented effectively into the FPGA-Xilinx Virtex2 XC2V6000 FF1157-4 chip.

The effects of CPU load & idle state on embedded processor energy usage

Device power consumption is a serious design consideration especially for embedded systems. By reducing the power consumption of a particular system, we could effectively prolong the runtime of the system, allowing for longer operational condition of a particular system. Previous studies have suggested that the power characteristics of a modern embedded processor have since been improved with manufacturers implementation of better energy-focused designs. Implementation of hardware optimization such as better clock and power gating have been shown to produce better energy usage during on-load and off-load processing. In this paper we benchmarked the energy use of a modern embedded processor and study the effects of idling time to the processor and system energy usage. We have found that the processor energy use is significantly reduced in the instant that the processor goes idle during the execution process. The idling time during a processing timeslice allows the processor to use significantly less energy without explicitly depending on a frequency scaling algorithm to reduce energy consumption. This power saving feature directly implemented inside the processor hardware have the possibility to render software based frequency scaling algorithm and DVFS method to be less effective in reducing energy usage.

Performance Investigation of Joint User-Proportional Fair Scheduling Algorithm in LTE-Advanced System with Carrier Aggregation

Carrier Aggregation (CA) is a promising technology that proposed by 3GPP in the latest LTEAdvanced (LTE-A) criterions in order to satisfy the future IMT-Advanced mobile networks demands. While CA allows aggregation of component carriers (CCs) dispersed within and transversely in diverse bands (intra/inter-band), CA is expected to offer a powerful boost to the user throughput in LTEAdvanced system. In addition, it will permit the achievement of the target peak data rates in excess of 1 Gbps in the downlink and 500 Mbps in the uplink in which the users has the right to use up to 100 MHz total of bandwidth. The mixture of LTE-A and LTE users within a multi-carrier LTE-A network may perhaps exist simultaneously. Each of them has various CA capabilities. The former has the ability to assign on multiple CCs, whereas the later can allocate on one CC. Moreover, they demand diverse QoS requirements which present new challenges to optimize the performance of LTE-Advanced system. Therefore, the choice of scheduling strategies plays a key role in guaranteeing desirable end to end system performance. The study of this paper will be beneficial for understanding the radio resource management (RRM) function with carrier aggregation feature. In addition, this article presents the Joint UserProportional Fair scheduling scheme (JUS-PF) for resource allocation and its impacts on two deployment scenarios which are LTE-A users and mixture (LTE/LTE-A) users’ scenario in terms of average user throughput, cell edge user throughput, and fairness.

Optimization of Vehicular Ad Hoc Network using Taguchi method

Vehicular Ad Hoc Network (VANET) is quite different from other ad hoc networks in term of functionality because of the variable node density, high node mobility, and unpredictable and harsh communication environment. There are two major applications VANET, namely safety applications and non-safety applications. In addition, network optimization is one way to maintain the existing protocols and other network parameter compare to design and implementing new improved protocols in which it too costly. Motivated with the reasons this paper presents an optimization of vehicular network for throughput, end-to-end delay and packet delivery ratio using Taguchi method. Highway scenario is chosen as the evaluation condition for this paper. For three performances evaluated, the highest rank value shows the different factors. For safety application which is delay-sensitive, routing protocols is the highest rank control factors. Non-safety application which is throughput sensitive, packet size is the main control factors.

A review and survey of routing techniques in transparent core optical networks: Evolution, perspectives and frontiers

In this survey, we presents a framework that proposes a guidelines and recommendation for the Routing Techniques perspectives in optical networks. Several subject are discussed in detail in this paper. A first important topic is the fundamental of Optical Routing techniques for network planning and optimization has recently attracted intensive research interest particularly in the area of intelligent control plane. A second important issues is the routing problem in networks with static, incremental and dynamic. In addition, we investigate several routing techniques by comparing in term of their operation, characteristics and mechanisms. Finally, this survey contributes to appropriate knowledge and challenges in legacy optical networks and towards future research development.

Hardware Implementation of Modeling Frequency Coded Serial Communication for Eurobalise Using ASK Module

This paper discusses about the modeling of frequency coded serial communication for the application of Eurobalise on hardware-based field programmable gate array (FPGA). The transceiver consists of FPGA and the ultra-high frequency (UHF) band amplitude shift keying (ASK) module. In the convention interface of the ASK transceiver module with the digital controller, noise has introduce into the channel. The noise in the output of ASK receiver has distorted the transmitted data causing the throughput of the wireless channel to be decreased. When the ASK module interfaces with the FPGA device, the noise from the output of the ASK receiver causing the receiving FPGA retarded. The purpose of the frequency coded serial data is to provide continuous specific frequency pulse train to the ASK transmitter. The original serial bit stream is then modulated in the pulse train with different frequency corresponding to the bit’s logic level. This technique has made the output of the ASK receiver to produce a very clean signal with extremely less noise. Hence, the receiver’s FPGA able to capture all the transmitted data accurately across traditional disciplinary boundaries, including computer hardware, algorithms, electronics interfacing and application domain.

Reducing Total Power Consumption and Total Area Techniques for Network-on-Chip Through Disable Cores and Routers Based on Clustering Method

Zarina Mohd Noh*, Abdul Rahman Ramli, Marsyita Hanafi, M Iqbal Saripan, Ridza Azri Ramlee 1,2,3,4 Department of Computer and Communication Systems Engineering, Faculty of Engineering, Universiti Putra Malaysia, 43400 UPM Serdang, Selangor, Malaysia 1,5 Fakulti Kejuruteraan Elektronik dan Kejuruteraan Komputer, Universiti Teknikal Malaysia Melaka (UTeM), Hang Tuah Jaya, 75450 Durian Tunggal, Melaka, Malaysia

Topology Design of Extended Torus and Ring for Low Latency Network-on-Chip Architecture

In essence, Network-on-Chip (NoC) also known as on-chip interconnection network has been proposed as a design solution to System-on-Chip (SoC). The routing algorithm, topology and switching technique are significant because of the most influential effect on the overall performance of Network-on-Chip (NoC). Designing of large scale topology alongside the support of deadlock free, low latency, high throughput and low power consumption is notably challenging in particular with expanding network size. This paper proposed an 8x8 XX-Torus and 64 nodes XX-Ring topology schemes for Network-on-Chip to minimize the latency by decrease the node diameter from the source node to destination node. Correspondingly, we compare in differences on the performance of mesh, full-mesh, torus and ring topologies with XX-Torus and XX-Ring topologies in term of latency. Results show that XX-Ring outperforms the conventional topologies in term of latency. XX-Ring decreases the average latency by 106.28%, 14.80%, 6.7 1%, 1.73%, 442.24% over the mesh, fully-mesh, torus, XX-torus, and Ring topologies.