Mohd Shahiman Sulaiman

Expert System for Power Quality Disturbance Classifier

Identification and classification of voltage and current disturbances in power systems are important tasks in the monitoring and protection of power system. Most power quality disturbances are non-stationary and transitory and the detection and classification have proved to be very demanding. The concept of discrete wavelet transform for feature extraction of power disturbance signal combined with artificial neural network and fuzzy logic incorporated as a powerful tool for detecting and classifying power quality problems. This paper employes a different type of univariate randomly optimized neural network combined with discrete wavelet transform and fuzzy logic to have a better power quality disturbance classification accuracy. The disturbances of interest include sag, swell, transient, fluctuation, and interruption. The system is modeled using VHSIC hardware description language (VHDL), a hardware description language, followed by extensive testing and simulation to verify the functionality of the system that allows efficient hardware implementation of the same. This proposed method classifies, and achieves 98.19% classification accuracy for the application of this system on software-generated signals and utility sampled disturbance events.

FPGA realization of multipurpose FIR filter

A multipurpose FIR filter has been designed and realized by field programmable gate arrays (FPGA) for real-time filtering applications. The design can accomplish an arbitrary filter frequency response and variable filter order up to 127. The coefficients are computed through the Hamming windowing technique. The model is capable of performing filtering operations, like lowpass, highpass, bandpass and bandstop based on selection that is embedded into the design. The filter is set to 8-bit signed data processing. Linear constant coefficient difference equation (LCCDE) has been used to filter the input data in time domain. The design is coded with VHDL to cope with the parallelism of digital hardware. Simulation, compilation and synthesis have been done to verify the validity of the design outputs. To test the correctness of the design the observed output is compared with the calculated output results from MATLAB implementation that confirms the effectiveness of the design.

A single clock cycle MIPS RISC processor design using VHDL

This paper describes a design methodology of a single clock cycle MIPS RISC Processor using VHDL to ease the description, verification, simulation and hardware realization. The RISC processor has fixed-length of 32-bit instructions based on three different format R-format, I-format and J-format, and 32-bit general-purpose registers with memory word of 32-bit. The MIPS processor is separated into five stages: instruction fetch, instruction decode, execution, data memory and write back. The control unit controls the operations performed in these stages. All the modules in the design are coded in VHDL, as it is very useful tool with its concept of concurrency to cope with the parallelism of digital hardware. The top-level module connects all the stages into a higher level. Once detecting the particular approaches for input, output, main block and different modules, the VHDL descriptions are run through a VHDL simulator, followed by the timing analysis for the validation, functionality and performance of the designated design that demonstrate the effectiveness of the design.

Iris recognition using neural network based on VHDL prototyping

This paper describes the development of a synthesizable VHDL model of a neural network application to recognize irises for user verification. Iris has unique features to be used as a biometric signature due to its speed, simplicity, accuracy, and applicability. Fourier transform is used to transform the image into data that can feed into the network. A two layer neural network is chosen with the input layer having three neurons, hidden layer having two neurons and the output layer having one neuron. The sigmoid function has been used as the activation function. The Iris recognition offers better alternative way of user verification. The Iris preprocessing had done in Matlab software and tested.

FPGA realization of backpropagation for stock market prediction

In this paper, we present the realization of backpropagation on Altera FLEX10K FPGA device for stock market prediction utilizing the parallelism that exists in the neural network architecture. This approach provides an increased speed of convergence of the network and accuracy for the stock market forecast. The stock market prediction neural network architecture comprises of three layers, input layer, hidden layer and output layer. There are three neurons in the input layer, two neurons in the hidden layer and one neuron in the output layer. Sigmoid transfer function is used for hidden layer and output layer neuron. Neuron for each of the backpropagation layer is modeled individually using behavioral VHDL. The layers are then connected using structural VHDL. This is followed by the timing analysis and circuit synthesis for the validation, functionality and performance of the designated circuit which supports the practicality, advantages and effectiveness of the proposed hardware realization for the applications.

Hardware prototyping of boolean function classification schemes for lossless data compression

In this paper, we present the realization of Boolean function classification schemes on Altera FLEX10K FPGA device for lossless data compression. The compression algorithm is performed by incorporating Boolean function classification into Huffman coding. This allows for more efficient compression because the data has been categorized and simplified before the encoding is done. The design is followed by the timing analysts and circuit synthesis for the validation, functionality and performance of the designated circuit which supports the practicality, advantages and effectiveness of the proposed hardware realization for the applications. The average compression ratio is 25% to 37.5% from numerous testing with various text inputs with a maximum clock frequency of 27.9 MHz

The hardware design of temperature controller based on fuzzy logic for industrial application employing FPGA

In this paper, we present the realization of a fuzzy logic-based temperature controller intended for industrial application on Altera FLEX10K FPGA device that allows for efficient hardware implementation. The system is built of four major modules called fuzzification, inference, implication and defuzzification. The composition method selected for the fuzzy model is the max-min composition while the Mamdani min operator was chosen as the implication method. Each module is modeled individually using behavioral VHDL and combined using structural VHDL. The timing analysis for the validation, functionality and performance of the model is performed using Aldec active HDL, and the logic synthesis was performed using Synplify. Simulation results show that the model has been tested successfully. The inferred maximum operating frequency is 5 MHz with a critical path of 199.3 ns.

A novel low-power high-speed programmable dual modulus divider for PLL-based frequency synthesizer

A low-power high-speed programmable dual modulus divider architecture is presented. The circuits three building blocks: prescaler, 2- and 5-bit programmable dividers; were designed using high-performance single-phase clocking latch-up circuits rather than the conventional latch-up circuits widely used in digital systems. The dividers operate based on the modulus control and parallel loading concepts, capable of operating within the division ratio of 32-127. The programmable dual-modulus divider with 2.4 GHz maximum operating frequency was designed using the 0.18-/spl mu/m CMOS technology. Post parasitics-extracted layout results verify that the total power dissipation was 2.3 mW (at 2.4 GHz, 1.8 V).

A balanced clock network design algorithm for clock delay, skew, and power optimization with slew rate constraint

A heuristic algorithm for optimized clock network design is presented. The algorithms for optimization of clock skew, delay, and power considering slew rate constraint for a balanced IC clock tree are implemented using a modified method of cautious approach. Algorithms developed are verified with the model of a real chip, i.e. post layout model of an FPGA chip. HSpice simulations at 115/spl deg/C, with CMOS 0.35 /spl mu/m models and parameters show a 60% reduction in the clock slew rate and a 23% improvement in the power dissipation when compared to the results of the initial, unoptimized chip.

The simultaneous logic and IDDQ testing of CMOS ICs with mixed-mode testing facility for sequential circuits

This paper presents an approach to design and develop a VLSI system for the simultaneous logic and IDDQ testing of CMOS ICs with mixed-mode testing facility for sequential circuits. The work involves the design of an interfacing unit on PCB containing interfacing circuits for parallel data exchange between a test processor and a microcomputer. This allows IDDQ measurement for every vector used for logic testing, performing logic testing simultaneously, providing a promising IDDQ fault coverage and reducing substantially the time and cost of testing. Three basic test development strategies are considered. They are functional test development, structural test development and physical defect test development. Mixed-mode testing facility is adopted to enhance the performance and reduce the testing time.