Mokhtar Nibouche

Application of fractals to the detection and classification of shoeprints

The most common clues left at a crime scene when a crime is committed are shoeprint impressions. These impressions are useful in the detection of criminals and the linking of crime scenes. A novel technique for use in the detection and classification of shoeprint impressions has been developed. The technique is based on fractal based feature extraction and pattern matching methods. The computerized system developed has been extensively tested on a large database of real shoeprint impressions and is robust to small variations of image orientations and/or translations.

Fast architectures for FPGA-based implementation of RSA encryption algorithm

In this work, new structures that implement RSA cryptographic algorithm are presented. These structures are built upon a modified Montgomery modular multiplier, where the operations of multiplication and modular reductions are carried out in parallel rather than interleaved as in the traditional Montgomery multiplier. The global broadcast of data lines is avoided by interleaving two or more encryption/decryption operations onto the same structure, thus making the implementation systolic and scalable. The digit approach has been adopted in This work. This methodology is based on varying the digit size and the level of pipelining of the structures. This parameterised approach presents the designer with an efficient way of choosing the architecture that suits better his/her requirements in terms of speed and area usage, an issue of critical importance to the resources-limited FPGA chips. The results of implementation using FPGA have shown that the proposed RSA structures outperformed those structures built around the traditional Montgomery multiplier in terms of speed, thanks to avoiding global lines broadcast.

FPGA-Based Discrete Wavelet Transforms System

Although FPGA technology offers the potential of designing high performance systems at low cost, its programming model is prohibitively low level. To allow a novice signal/image processing end-user to benefit from this kind of devices, the level of design abstraction needs to be raised. This approach will help the application developer to focus on signal/image processing algorithms rather than on low-level designs and implementations. This paper presents a framework for an FPGA-based Discrete Wavelet Transform system. The approach helps the end-user to generate FPGA configurations for DWT at a high level without any knowledge of the low-level design styles and architectures.

High speed FPGA implementation of RSA encryption algorithm

In this paper, new structures that implement RSA cryptographic algorithm are presented. These structures are built using a modified Montgomery modular multiplier, where the operations of multiplication and modular reductions are carried out in parallel rather than interleaved as in the traditional Montgomery multiplier. The global broadcast data lines are avoided by interleaving two operations into the same structure, thus making the implementation systolic. The results of implementation in FPGA have shown that the proposed RSA structures outperformed those structures built around a traditional Montgomery multiplier in terms of speed. In terms of area usage, an area-efficient architecture is shown in this paper that has the merit of having a high speed and a reduced area usage when compared with other architectures.

New architectures for serial-serial multiplication

Traditional serial-serial multiplier structures suffer from an inefficient generation of partial products, which leads to hardware overuse and slow speed systems. In this paper, two new architectures for fully serial multiplication are presented. To the best of our knowledge, the first structure is the first fully serial multiplier reported in the literature with comparable performance-in terms of speed-to existing serial-parallel multipliers. The second structure requires an extra multiplexer in the clock path thus making it slower, but has the merit of reducing the latency of the multiplier. Both structures are systolic and need near communication links only. Compared with available architectures, an FPGA based implementation has shown an increase in the speed of the multipliers by about 200% for the first structure and 150% for the second structure.

An FPGA-based wavelet transforms coprocessor

Although FPGA technology offers the potential of designing high performance systems at low cost for a wide range of applications, its programming model is prohibitively low level requiring either a dedicated FPGA-experienced programmer or basic digital design knowledge. To allow a signal/image processing end-user to benefit from this kind of device, the level of design abstraction needs to be raised, even beyond a hardware description language level (e.g. VHDL). This approach will help the application developer to focus on signal/image processing algorithms rather than on low-level designs and implementations. This paper aims to present a framework for an FPGA-based coprocessor dedicated to discrete wavelet transforms (DWT). The proposed approach will help the end-user to generate FPGA configurations for DWT at the highest level without any knowledge of the low-level design styles and architectures.

New iterative algorithms and architectures of modular multiplication for cryptography

Algorithms and architectures for performing modular multiplication operations, which is central to crypto-system and authentication schemes, are important in todays needs of secure communications. This paper presents two new iterative algorithms for modular multiplication. The implementation of these algorithms yields to scalable architectures that can be used for any modulus without altering the design. In addition, the Radix-2 algorithm shows almost similar features when compared with similar architectures available in the literature. Furthermore, the radix-4 algorithm can be used to develop higher radix algorithms since it only requires the use of powers of two of the modulus.

A new pipelined digit serial-parallel multiplier

Digit-serial architectures obtained using traditional unfolding and folding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, a novel approach for the design of pipelined digit serial-parallel multipliers is presented.

Design and implementation of a wavelet based system

Compared to traditional transforms such as the FFT and the DCT, the wavelet transform is seen rather as the framework of a transform. From this framework, different wavelets can be derived depending on the type of the basis, the number of coefficients and different other parameters. The aim of this paper to introduce methodology and an environment for a rapid design of wavelet filters for both 1-D and 2-D applications.

Bit-level architectures for Montgomery's multiplication

Algorithms and architectures for performing modular multiplication operations are important in cryptography and Residue Number System. In this paper Montgomerys algorithm has been broken into two concurrent no-interleaved multiplication operations. The architectures derived from this algorithm are systolic and need near communication links only. Thus, very well suited for VLSI implementation. The presented architectures offer a great flexibility of finding the best trade-off between hardware cost and throughput rate by changing the digit size.