Monica Figueiredo

Predicting noise and jitter in CMOS inverters

Jitter in CMOS technologies depend on several physical and design parameters, which are expected to change with scaling. Also, some parameters will have to change (by the introduction of enhancement techniques) in order to meet the desired performance goals for each new generation. The impact of each one of these parameters is here evaluated in order to give some insight on the jitter generation, amplification and coupling phenomena in actual and future designs. The work is based on AMS (0.8 um and 0.35 um) and UMC (180 nm and 130 nm) models for high performance, minimum sized transistors. Also, data from ITRS has been used to predict jitter dependency on the various parameters in deep-submicron CMOS generations.

Noise and Jitter in CMOS Digitally Controlled Delay Lines

Analysing the impact of noise sources on the random instantaneous delay of a basic CMOS delay element is important for understanding the performance of systems that employ them, like voltage controlled delay lines or buffered clock distribution networks. This paper presents a model for the analysis of noise induced jitter in CMOS delay cells and delay lines. Because the increasing switching noise levels is becoming a serious impairment to the reliable use of analogue controlled devices inside high frequency digital VLSI circuits, this work focus primarily on digitally controlled delay lines. For these circuits, the output capacitance and drivability of delay elements are key parameters for the design of low jitter delay lines. Simulation results are presented for a 0.35mum CMOS technology.

A real-time platform for collaborative research on Visible Light Communication

This paper reports the implementation and performance results of a real-time Visible Light Communication platform. The platform uses a high-level software abstraction architecture where the algorithms are developed and tested in MATLAB, using a modular architecture. With this modular approach it is very easy to add/remove blocks, making it amenable to collaboration with other groups with interest in this field, offering a real-time test bed to evaluate the performance of different modules, algorithms and optical front-ends, which is currently not available. The physical layer is based on DCO-OFDM and is implemented in a Xilinx Virtex-6 FPGA. We explore the optical front-end out-of-band bandwidth to transmit, showing the usefulness of adopting OFDM-based modulations schemes for VLC. Our system transmits at 2m over an indoor free space channel with 12MHz bandwidth, with more than 23dB gain difference, using QPSK, thus achieving 24Mbit/s with a BER smaller than the usual 3.8×10-3 limit.

Live demonstration: 150Mbps+ DCO-OFDM VLC

This demonstration showcases the potential of OFDM-based Visible Light Communication (VLC) systems for indoor high-speed communications using off-the-shelf LEDs, suitable for illumination. The physical layer was implemented in a Xilinx Virtex-6 FPGA using System Generator. It was designed with a modular architecture, enabling collaboration with other groups with interest in this field. This demonstration explores the optical front-end out-of-band bandwidth to transmit, showing the usefulness of OFDM-based schemes. Using 64QAM and 25MHz modulation bandwidth, it is possible to transmit over 50cm at 150Mbit/s with a BER smaller than the usual 3.8×10-3 limit.

Dynamic jitter accumulation in clock repeaters considering power and ground noise correlations

This paper discusses the mechanism behind dynamic jitter accumulation in clock repeaters, considering the impact of power supply noise correlations. We show that differential and common mode noise have a different impact on jitter accumulation, depending on correlations between cascaded repeater stages. We also propose a simple accumulation model that can be used to replace time-consuming transient noise simulations. Besides providing an useful insight regarding the impact of noise correlations on jitter accumulation, the models accuracy is shown to be within 10% of SPICE results.

Time precision comparison of digitally controlled delay elements

This paper compares the time precision of different digitally controlled delay cells. Other design metrics as delay, signal integrity, power and area are also considered. The precision is evaluated by the cells uncertainty, given as the ratio between jitter and time delay, considering both thermal and power supply noise. The comparison is based on circuit simulation, in a 180nm technology, using the SPECTRE tool from Cadence. The comparison results will help the designer to choose the most appropriate delay cell for low uncertainty design.

Lighting the Wireless World: The Promise and Challenges of Visible Light Communication

Light-emitting diodes (LEDs) are becoming increasingly ubiquitous. They can be found in illumination appliances, phones, TVs, advertising panels, dashboards, and traffic signals, among others. Most illumination applications are becoming LED based, mainly due to their long operational lifetime and high energy efficiency, which is nowadays higher than 100 lm/W [1]. Other benefits include enhanced sustainability, a compact form factor, easier maintenance, and lower cost. For these reasons, LED lighting is expected to have a market share of 84% in the general illumination market by 2030 [2]. However, there is another characteristic that is not being fully exploited: LEDs are capable of switching their light intensity at a rate that is imperceptible to the human eye. This property has been used for dimming purposes but can also be utilized in the opportunistic deployment of value-added services based on visible light communication (VLC).

Electronic shelf labeling employing visible light communication concepts

This paper discusses the usage of visible light communication concepts for Electronic Shelf Labeling Devices (ESLD), using unmodified smart phones. Visible light communication enables novel and interesting approaches to the design of these devices, able to address application scenarios that have not yet been explored. Amongst these novel approaches, it is worthwhile highlighting the feasibility to offer easy integration of social networking concepts, and the inherent ability to explore communication means supported by the lighting installation. The achieved results show that these novel electronic shelf labeling devices are able to offer good quality of service support, with nearly optimal bit error rates under normal illumination levels.

A dynamic jitter model to evaluate uncertainty trends with technology scaling

Clock jitter can no longer be considered negligible when compared to clock skew. Its unpredictability and high-frequency content makes it an increasingly limiting factor to performance in modern digital systems. In this paper, we investigate dynamic jitter and uncertainty trends, as technology continues scaling to the nanometric region. Simulation results are used to derive heuristic metrics for the sensitivity of a generic repeater to dynamic variability sources. These metrics are then used to discuss clock precision degradation with technology scaling. Using parameters that can be easily obtained, the proposed model can be useful to assess the expected behavior of existing and future technologies in terms of clock precision. Also, it provides a valuable insight regarding the key circuit parameters responsible for dynamic jitter insertion.

Clock repeater characterization for jitter-aware clock tree synthesis

This paper presents a simple jitter model for clock repeaters. The model is scalable and technology independent, which makes it suitable for integration in current clock tree synthesis algorithms. It is based on the timing characterization of a reference inverter, which can be performed for different process corners to account for process variability. Simulation results show that the model is accurate to within 10% for the most common inverter and NAND based repeaters.