Luis Nero Alves

Fast Motion Estimation Algorithm for HEVC

Motion Estimation is an essential process in many video coding standards like MPEG-2, H.264/AVC and HEVC. Despite Motion Estimation has been used at the encoder, it is expected to be used in future consumer devices in the distributed video coding architectures. But the Motion Estimation itself consumes more than 50% coding complexity or time to encode. To reduce the computation time, many fast Motion Estimation Algorithms were proposed and implemented. The present paper proposes a new fast ME algorithm which outperforms the fast ME algorithm implemented in HEVC reference software HM.

Visible light communication for intelligent transportation in road safety applications

This paper discusses the implementation of a light emitting diode based visible light communication system, for intelligent transportation in road safety applications. The signal processing of both, transmitter and receiver are realized in a field programmable gate array using two Spartan-3E development kits. The implemented modulation scheme is based on direct sequence spread spectrum techniques. The performance of the overall system is evaluated and results are presented. It is found that the system is well suited for traffic broadcast at low data rate and medium range. The simulation results also show that spread spectrum modulation techniques mitigate the effect of noise produced by ambient artificial light sources.

Visible light communications in intelligent transportation systems

Emerging intelligent transportation systems (ITS) are based on several technologies. A new concept of integrating visible light communications (VLC) in ITS is introduced in this paper. VLC in ITS is a cost effective method of implementation. This paper presents a VLC broadcast system considering LED-based traffic lights. It discusses the integration of traffic light road side unit (RSUs) within the existing ITS architecture. A prototype demonstrator of the designed VLC systems is also presented. A robust modulation technique based on direct sequence spread spectrum (DSSS) sequence inverse keying (SIK) has been implemented to minimize the effect of noise sources. Experimental results show data communication range of over 40m with 200mm custom designed traffic light, even during bright sun light.

Visible Light Communication System for outdoor applications

This paper presents a Visible Light Communication (VLC) system architecture suitable for outdoor applications. VLC usages in outdoor scenarios are facing new opportunities raised by the increasing trends on the usage of LEDs. Traffic light signals and public illumination systems are two application examples, where VLC can show its merits. These scenarios pose several challenges due to the fact that it is difficult to control environmental conditions. Thus, VLC systems able to operate under these conditions need to employ robust modulation schemes. This paper proposes the usage of direct sequence spread spectrum to combat noise and interference. The implemented prototype demonstrates that it is feasible to achieve more than 40m communication range for low data rate applications even in the presence of significant optical noise levels.

A novel SAD architecture for variable block size motion estimation in HEVC video coding

Motion estimation (ME) is one of the critical and most time consuming tasks in video coding. The increase of block size to 64x64 and introduction of asymmetric motion partitioning (AMP) in HEVC makes variable block size motion estimation more complex and therefore requires specific hardware architecture for real time implementation. The ME process includes the calculation of SAD (Sum of Absolute Difference) of two blocks, the current and the reference blocks. The present paper proposes low complexity SAD (Sum of Absolute Difference) architecture for ME of HEVC video encoder, which is able to exploit and optimize parallelism at various levels. The proposed architecture was implemented in FPGA, and compared with other non-parallel SAD architectures. Synthesis results show that the proposed architecture takes fewer resources in FPGA when compared with results from non-parallel architectures and other contributions.

High speed SAD architectures for variable block size motion estimation in HEVC video coding

HEVC is the latest video coding standard aimed to compress double to that of its predecessor standard H.264/AVC at the cost of increased coding complexity. Motion Estimation (ME) is one of its critical tools in the encoder whose complexity drastically increases due to the increase in coding block size to 64×64 and due to the introduction of Asymmetric Motion Partitioning (AMP). Hence it requires specific hardware architectures for real time implementation. The bottleneck of ME tool is the SAD (Sum of Absolute Difference) circuit architecture which calculates SAD between current block and reference block pixels. The present paper proposes and implements three SAD architectures in FPGA. Synthesis results show that one of the proposed architectures outperforms when compared to results of other contributions, despite supporting all block modes of HEVC.

Maximizing bandwidth in CCII for wireless optical applications

This paper discusses bandwidth problems associated with the usage of second-generation current conveyors in wireless optical systems, and presents a new current amplifier with wide bandwidth and large input dynamic range, developed for Fast Ethernet wireless applications. This current amplifier is used to interconnect low cost photodetectors (with large intrinsic capacitance) with transimpedance amplifiers, overcoming typical bandwidth limitations imposed by the input transducers. This current adaptation concept has proved to be adequate for increasing both bandwidth and dynamic range of traditional optical interfaces. The proposed current amplifier architecture is based on a CCII with reduced input impedance and achieves, for a 10 pF input photodetector, a maximum gain of 18 dB with a 130 MHz bandwidth, with a noise floor of 9.2 pA//spl radic/Hz. The expected input dynamic range is larger than 65 dB.

Complexity reduction methods for fast motion estimation in HEVC

Motion estimation is one of the most demanding and complex tools in block based video encoders. Variable block size motion estimation (ME) and multiple reference frames in H.264/AVC make motion estimation even more complex and time consuming. In HEVC, the complexity is even higher since there are more block sizes. This paper presents an analysis of various tools involved in some fast ME algorithms and proposes some improvements to them in order to achieve a novel fast hybrid algorithm. The proposed algorithm has been tested with HEVC reference software. Simulation results show that the algorithm achieves up to 44.7% decrease in ME complexity when compared to the fast ME algorithm (Test Zone Search or TZSearch) and up to 99% reduction in ME complexity compared to full search algorithm with negligible loss in PSNR and bitrate. Motion estimation is one of the most complex tools in block based video encoders.In HEVC, the motion estimation complexity is even higher since there are more block sizes.TZSearch algorithm is the fast motion estimation algorithm in HEVC reference software.This paper reduces the complexity of TZSearch ME algorithm upto 44.7%.The overall RD performance loss is negligible despite decrease in the complexity.

A low-noise CMOS front-end for TOF-PET

An analogue CMOS front-end for triggering and amplification of signals produced by a silicon photomultiplier (SiPM) coupled to a LYSO scintillator is proposed. The solution is intended for time-of-flight measurement in compact Positron Emission Tomography (TOF-PET) medical imaging equipments where excellent timing resolution is required ( ≈ 100ps). A CMOS 0.13μm technology was used to implement such front end, and the design includes preamplification, shaping, baseline holder and biasing circuitry, for a total silicon area of 500x90 μm. Waveform sampling and time-over-threshold (ToT) techniques are under study and the front-end provides fast and shaped outputs for time and energy measurements. Post layout simulation results show that, for the trigger of a single photoelectron, the time jitter due to the pre-amplifier noise can be as low as 15 ps (FWHM), for a photodetector with a total capacitance of 70 pF. The very low input impedance of the pre-amplifier ( ≈ 5Ω) allows 1.8 ns of peaking time, at the cost of 10 mW of power consumption.

Design, development and performance analysis of DSSS-based transceiver for VLC

This paper addresses and implements a Direct Sequence Spread Spectrum (DSSS) transceiver for Visible Light Communication (VLC) systems based on FPGA. A transceiver was implemented including a transmitter capable of driving an array of light emitting diodes (LED) and a Pseudo-Noise (PN) matched decorrelator. The receiver architecture uses a discrete FIR correlator for data synchronization and acquisition. In this paper, a novel and simple PN code with a 10 bit sequence length is developed. This code offers a similar performance to the popular Barker code; however, it has a simple design. The used FPGA resources are presented along with a performance analysis.