Montserrat Bóo

High-performance VLSI architecture for the Viterbi algorithm

The Viterbi (1967) algorithm (VA) is known to be an efficient method for the realization of maximum-likelihood (ML) decoding of convolutional codes. The VA is characterized by a graph, called a trellis, which defines the transitions between states. To define an area efficient architecture for the VA is equivalent to obtaining an efficient mapping of the trellis. We present a methodology that permits the efficient hardware mapping of the VA onto a processor network of arbitrary size. This formal model is employed for the partitioning of the computations among an arbitrary number of processors in such a way that the data are recirculated, optimizing the use of the PEs and the communications. Therefore, the algorithm is mapped onto a column of processing elements and an optimal design solution is obtained for a particular set of area and/or speed constraints. Furthermore, the management of the surviving path memory for its mapping and distribution among the processors was studied. As a result, we obtain a regular and modular design appropriate for its VLSI implementation in which the only necessary communications between processors are the data recirculations between stages.

Hardware support for adaptive subdivision surface rendering

Adaptive subdivision of triangular meshes is highly desirable for surface generation algorithms including adaptive displacement mapping in which a highly detailed model can be constructed from a coarse triangle mesh and a displacement map. The communication requirements between the CPU and the graphics pipeline can be reduced if more detailed and complex surfaces are generated, as in displacement mapping, by an adaptive tessellation unit which is part of the graphics pipeline. Generating subdivision surfaces requires a large amount of memory in whicmultiple arbitrary accesses are required to neighbouring vertices to calculate the new vertices. In this paper we present a meshing scheme and new architecture for the implementation of adaptive subdivision of triangular meshes that allows for quick access using a small memory making it feasible in hardware, while at the same time allowing for new vertices to be adaptively inserted. The architecutre is regular and characterized by an efficient data management that minimizes the data storage and avoids the wait cycles that would be associated with the multiple data accesses required for traditional subdivision. This architecture is presented as an improvement for adaptive displacement mapping algorithms, but could also be used for adaptive subdivision surface generation in hardware.

VLSI implementation of an edge detector based on Sobel operator

We present the design and implementation of the Sobel operator in an application specific integrated circuit. Systolic processor arrays were employed for an efficient exploitation of the advantages of VLSI technology. The architecture obtained is highly regular and simple. The performance of the architecture is improved by means of the use of carry save arithmetic. The chip was implemented using 1 /spl mu/m CMOS technology and the final area is 10 mm/sup 2/. The resulting chip provides the values for the pixels of the gradient images (rows and columns) alternatively each clock cycle with a 20 cycle latency. The maximum operating frequency is 50 MHz and, consequently, it is an adequate design for real time image processing.<<ETX>>

A novel design of a two operand normalization circuit

This paper presents a new design for two operand normalization. The two operand normalization operation involves the normalization of at least one of two operands by left shifting both by the same amount. Our design performs the computation of the shift by making an OR of the bits of both operands in a tree network, encoding the position of the first nonzero bit. The encoded position is obtained most significant bit first, and then there is an overlapping with the shifting operation. The design we propose replaces two leading zero detector circuits and a comparator, that are present in the conventional approach. Our scheme demonstrates to be more area efficient than the conventional one. The circuit we propose is useful in floating point complex multiplication and COordinate Rotation DIgital Computer (CORDIC) processors.

The split-and-merge method in general purpose computation on GPUs

The split-and-merge method is an algorithm design paradigm sometimes used in the field of parallel computing. It is applied to multilevel algorithms such as the wavelet transforms and some tridiagonal system solvers. In this paper we present the application of the method in the context of general purpose computation on GPUs. The split-and-merge method allows us to efficiently use the CUDA parallel programming model, where a multithreaded program is partitioned into blocks of threads that execute independently from each other. Thus we can solve the data dependency problem at the block boundaries and efficiently take advantage of the memory hierarchy of the GPU. The results obtained show a significant acceleration compared with the direct implementation of the algorithms on the GPU.

Extended hybrid meshing algorithm for multiresolution terrain models

Hybrid terrains are a convenient approach for the representation of digital terrain models, integrating heterogeneous data from different sources. In this article, we present a general, efficient scheme for achieving interactive level-of-detail rendering of hybrid terrain models, without the need for a costly preprocessing or resampling of the original data. The presented method works with hybrid digital terrains combining regular grid data and local high-resolution triangulated irregular networks. Since grid and triangulated irregular network data may belong to different datasets, a straightforward combination of both geometries would lead to meshes with holes and overlapping triangles. Our method generates a single multiresolution model integrating the different parts in a coherent way, by performing an adaptive tessellation of the region between their boundaries. Hence, our solution is one of the few existing approaches for integrating different multiresolution algorithms within the same terrain model, achieving a simple interactive rendering of complex hybrid terrains.

Unified Hybrid Terrain Representation Based on Local Convexifications

Hybrid digital terrain models represent an effective framework to combine and integrate terrain data with different topology and resolution. Cartographic digital terrain models typically are constituted by regular grid data and can be refined by adding locally TINs that represent morphologically complex terrain parts. Direct rendering of both data sets to visualize the digital terrain model would generate geometric discontinuities as the meshes are disconnected. In this paper we present a new meshing scheme for hybrid terrain representations. High quality models without discontinuities are generated as the different representations are softly joined through an adaptive tessellation procedure. Due to the complexity of the algorithms involved in the tessellation procedure, we propose a mixed strategy where part of the information is pre-computed and efficiently encoded. This way, for rendering the model, the tessellation information has to be decoded and only additional simple operations have to be performed.

A meshing scheme for efficient hardware implementation of butterfly subdivision using displacement mapping

Displacement mapping is an effective technique for encoding the high levels of detail of surface models using coarse triangle meshes and displacement maps. These maps are 2D representations containing the distances between the coarse mesh and the surface to represent. Displacement maps have been used in many applications such as ray tracing, image warping, and volume rendering. In this article, we propose modifications to our previous grouping strategy, a new subdivision strategy based on the Modified Butterfly algorithm and new heuristics for the adaptive subdivision procedure, and, finally, the corresponding modifications on our hardware proposal. A meshing scheme and an adaptive subdivision strategy based on displacement mapping reduce the bottleneck between the CPU and graphics pipeline common in high-performance graphics systems.

Efficient parallel implementations for surface subdivision

Achieving an efficient surface subdivision is an important issue today in computer graphics, geometric modeling, and scientific visualization. In this paper we present two parallel versions of the Modified Butterfly algorithm. Both versions are based on a coarse-grain approach, that is, the original mesh is subdivided into small groups and each processor performs the triangles subdivision for a set of groups of the mesh. First approach sorts the groups in decreasing order of number of triangles per group, and then the sorted groups are cyclically distributed on the processors in order to achieve a good load distribution. In the second parallel version the processors can dynamically balance the work load by passing groups from heavier loaded processors to lighter ones, achieving in that way a better load balance. Finally, we evaluate the algorithms on two different systems: a SGI Origin 2000 and a Sun cluster. Good performances in terms of speedup have been obtained using both static and dynamic parallel implementations.

Memory Hierarchy Optimization for Large Tridiagonal System Solvers on GPU

Nowadays GPUs are commodity hardware containing hundreds of cores and supporting thousands of threads that can be used to accelerate a wide range of applications. From a programmers perspective, GPUs offer a stream processing model which requires the application of new techniques to exploit their capabilities. In this paper we present the application of the split-and-merge technique to the following parallel tridiagonal system solvers on the GPU: cyclic reduction and recursive doubling. The split-and-merge technique naturally splits the algorithm flow in parallel paths that can be solved in shared memory, and later merged in global memory. In this way, we can solve large systems of equations efficiently exploiting the memory hierarchy of the GPU. The results obtained show a significant acceleration compared with the direct implementation of the algorithms on the GPU.