Moon-Key Lee

A fast array architecture for block matching algorithm

The block-matching motion estimation is the most popular method for motion-compensated coding of image sequence. Based on two dimensional systolic array, VLSI architecture for an implementation of full-search block matching algorithm is described. The proposed architecture has the following advantages: (1) it allows serial data inputs to save pin counts but performs parallel processing. (2) It is flexible in adaptation to the dimensional change of search window with simple control logic. (3) It has no idle time during the operation. (4) It can operate in real time for videoconference application and EDTV application. (5) It is modular and regular in design, and thus suitable for VLSI implementation.<<ETX>>

A VLSI array processor for 16-point FFT

An implementation of a two-dimensional array processor for fast Fourier transform (FFT) using a 2- mu m CMOS technology is presented. The array processor, which is dedicated to 16-point FFT, implements a 4*4 mesh array of 16 processing elements (PEs) working in parallel. Design considerations in both the chip level and the PE level are examined. A layout design methodology based on bit-slice units (BSUs) results in a very simple design, easy debugging, and a regular interconnection scheme through abutment. It contains about 48,000 transistors on an area of 53.52 mm/sup 2/, excluding the 83-pad area, and operation is on a 15-MHz clock. The array processor performs 24.6 million complex multiplications per second, and computes a 16-point FFT in 3 mu s. >

Reusable embedded debugger for 32 bit RISC processor using the JTAG boundary scan architecture

The traditional debug tools for chip tests and software developments need huge investment and plenty of time. These problems can be overcome by an embedded debugger based the JTAG boundary scan architecture. Thus, the IEEE 1149.1 standard is adopted by ASIC designers for testability problems. We designed the RED (reusable embedded debugger) using the JTAG boundary scan architecture. The proposed debugger is applicable for not only chip test but also software debugging. Our debugger has an additional hardware module (EICEM: embedded ICE module) for more critical real-time debugging.

Efficient random vector verification method for an embedded 32-bit RISC core

Processors require both intensive and extensive functional verification in their design phase to satisfy their general purposability. The proposed random vector verification method for CalmRISC/sup TM/-32 core meets this goal by contributing complementary assistance for conventional verification methods. It adopts a cycle-accurate instruction level simulator as a reference model, runs simulation in both the reference and the target HDL and reports errors if any difference is found between them. These processes are automatically performed in the unified environment. The instruction level simulator, the core part in the verification environment is able to simulate almost every aspect of RISC processors from functional behavior of each opcode to timing details in the pipeline flow in fast speed. Its design style from microprogramming scheme also makes its structure modular and flexible.

CalmRISC/sup TM/-32: a 32-bit low-power MCU core

Architecting todays embedded processor core faces several important design challenges: low power, high performance, and system-on-a-chip considerations. Moreover, support for high-level language constructs and operating systems becomes increasingly critical for acceptance to various applications. CalmRISC/sup TM/-32 effectively meets these challenges by incorporating a carefully designed instruction set, an energy-efficient pipeline design, debugging support with trace mode/CalmBreaker/sup TM/ (an in-circuit debugger), and a generic, yet efficient coprocessor interface. Using a 0.25 /spl mu/m static CMOS standard cell library and compiled datapath cells, the first implementation of CalmRISC/sup TM/-32 operates at 130 MHz (under worst conditions) and consumes 150 /spl mu/A/MHz at 2.5 V. This paper presents a brief description of the instruction set, the overall microarchitecture, and the coprocessor interface of CalmRISC/sup TM/-32.

A Fully Programmable Systolic Pipelined Digital Video Encoder For NTSC/PAL/PALplus Compatibility On A 4:3 Screen

An encoder is proposed that supports NTSC and PAL systems. In addition, it also permits the PALplus standard mode, that is compatible to a 16:9 wide screen, on a 4:3 screen. In order for this to be realized the vertical and horizontal synchronous timing are fully programmable and the encoder is designed in a systolic pipelined architecture with a double pixel clock to increase the internal processing speed. Also, we have mainly concentrated on reducing the gate counts of the submodules such as the letter-box converter, color converter matrix, low pass filter, interpolator, and color modulator. The encoder can accept RGB and YCbCr as the input pixel signal with a speed of 10-15 Mpps. The outputs are a Y/C (S-video) signal and a composite signal. We have modeled the encoder in Verilog-HDL and verified its overall operation by feeding the top module with a color bar test signal. The encoder, which was implemented by 0.6 /spl mu/m CMOS technology, contains about 42 k gates.

Allocation of multiport memories in ASIC data path synthesis

At present, datapath synthesis techniques produce a design with a large number of isolated registers. Allocation of memory modules to implement these resisters are usually left to the designer. This paper presents new approach to the allocation of multiport memories which minimizes hardware costs in ASIC datapath synthesis. The proposed approach, AMD, considers not only the access requirements of registers but also the lifetime of registers. The objective is to minimize the requirement of registers and multiport memory modules under a given resource constraints simultaneously. The minimization problem has been modeled as a 0-1 integer linear programming problem. This approach is illustrated with an example.<<ETX>>

Low power motion estimation algorithm based on temporal correlation and its architecture

We propose architecture of low power motion estimation algorithm. There are two types of MB (macro block) modes in the proposed algorithm (fast MB mode and normal MB mode). In the fast MB mode, the motion vector found from the previous frame is utilized in the next frame. This mode can be adopted in the conventional fast motion estimation algorithm, and as a result, the computational power is reduced by 40%. In normal the MB mode, among the conventional fast search algorithms, we take the 4SS (four step search), and introduce an additional search method called a center-focused search in the step to increase the PSNR level. We then, implement the corresponding PE (processing element) architecture that gives the hardware performance improvement. The new motion estimation architecture is especially efficient for mobile phone and video conferencing applications in which there is not much motion.

Safety and efficacy of tuberculin skin testing with microneedle MicronJet600™ in healthy adults

SETTING Intradermal injection using a syringe and needle is generally accepted as the most accurate method for the tuberculin skin test (TST). However, the Mantoux technique using a conventional needle is often difficult to perform reliably, affecting testing results and safety. OBJECTIVE We evaluated the efficacy and safety of a novel intradermal injection device, the MicronJet600(TM) microneedle, compared with conventional injection in terms of skin reactivity to the TST. DESIGN A prospective, open-label clinical study was conducted. The TST was administered by both methods in the same subject. For pain assessment, participants filled in a visual analogue scale (VAS) after each TST. Any side effects due to TST or injections were observed. RESULTS TST reaction rates (cut-off ⩾5 mm) from microneedles and needles were respectively 44.0% and 47.2%, with no significant difference between the two. Furthermore, agreement of positivity between the two methods was excellent with both 5 mm and 10 mm cut-off values. However, the level of pain experienced when microneedles were used for TST was significantly lower than with conventional needles. No adverse effects were attributed to the MicronJet device. CONCLUSION The novel microneedle device used for TST in this study was effective, safe and less painful in healthy adult volunteers.

Embedded Processor Validation Environment Using a Cycle-Accurate Retargetable Instruction-Set Simulator

In the advent of System-on-Chip (SoC) technology, validation scope is further expanded from a single core to the system. Modules are also substituted by application specific instruction-set processors (ASIP) in order to raise abstraction level of systems from signals to instructions. As embedded processors are diversified according to their specific application, they suffer from an increasing number of irregular constraints and architectural idiosyncrasies. They also have control paths of pipeline which shows quite complicated timing. In order to alleviate these design complexities, validation must take retargetability and cycle-accuracy into consideration. We have thus proposed efficient embedded processor validation environment (EPVE) using a cycle-accurate retargetable instruction-set simulator (CARISS) as a reference model. The designed CARISS is based on an architecture description language (ADL), which provides improved retargetability for instruction-set machines. It also uses a scheduling method which can capture complex processor behavior more accurately than the ones used by the previous ADLs. We have applied the proposed EPVE for the 32bit embedded processors and investigated effectiveness of our approach by analyzing statistics on detected errors.